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Features
* 80C52 Compatible
- 8051 Instruction Compatible - Four 8-bit I/O Ports (44 Pins Version) - Three 16-bit Timer/Counters - 256 bytes Scratch Pad RAM - 11 Interrupt Sources With 4 Priority Levels ISP (In-System Programming) Using Standard VCC Power Supply Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply Boot ROM Contains Serial Loader for In-System Programming High-speed Architecture - In Standard Mode: 40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only) - In X2 Mode (6 Clocks/Machine Cycle) 20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution) 30 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only) 128K bytes On-chip Flash Program/Data Memory - 128 bytes Page Write with auto-erase - 100k Write Cycles On-chip 8192 bytes Expanded RAM (XRAM) - Software Selectable Size (0, 256, 512, 768, 1024, 1792, 2048, 4096, 8192 bytes) Dual Data Pointer Extended stack pointer to 512 bytes Variable Length MOVX for Slow RAM/Peripherals Improved X2 Mode with Independant Selection for CPU and Each Peripheral Keyboard Interrupt Interface on Port 1 SPI Interface (Master/Slave Mode) 8-bit Clock Prescaler Programmable Counter Array with: - High Speed Output - Compare/Capture - Pulse Width Modulator - Watchdog Timer Capabilities Asynchronous Port Reset Two Full Duplex Enhanced UART with Dedicated Internal Baud Rate Generator Low EMI (inhibit ALE) Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag Power Control Modes: Idle Mode, Power-down Mode Power Supply: 2.7V to 5.5V Temperature Ranges: Industrial (-40 to +85C) Packages: PLCC44, VQFP44
* * * *
8-bit Flash Microcontroller AT89C51RE2
* * * * * * * * * *
* * * * * * * *
Description
AT89C51RE2 is a high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit microcontroller. It contains a 128 Kbytes Flash memory block for program. The 128 Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The AT89C51RE2 retains all features of the Atmel 80C52 with 256 bytes of internal RAM, a 10source 4-level interrupt controller and three timer/counters. In addition, the AT89C51RE2 has a Programmable Counter Array, an XRAM of 8192 bytes, a Hardware Watchdog Timer, SPI and Keyboard, two serial channels that facilitates multiprocessor communication (EUART), a speed improvement mechanism (X2 mode) and an extended stack mode that allows the stack to be extended in the lower 256 bytes of XRAM. The fully static design of the AT89C51RE2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The AT89C51RE2 has 2 software-selectable modes of reduced activity and 8-bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the AT89C51RE2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers. Table 1. Memory Size and I/O pins
AT89C51RE2 PLCC44 VQFP44 Flash (bytes) 128K XRAM (bytes) 8192 TOTAL RAM (bytes) 8192 + 256 I/O 34
2
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AT89C51RE2
Block Diagram
Figure 1. Block Diagram
Keyboard RxD_0 RxD_1 (1) BOOT Regulator 4K x8 POR / PFD ROM TxD_0 T2EX VCC PCA Vss TxD_1
ECI
T2
(2) (2) XTALA1 XTALA2 XTALB1(1) XTALB2 ALE/ PROG PSEN EA RD WR (2) (2) Timer 0 Timer 1 INT Ctrl CPU
C51 CORE
(1)
(1) (1)
(1)
(3) (3)
EUART
RAM 256x8
Flash 128Kx8
XRAM
8192 x 8
PCA
Watch Dog Timer2 Keyboard POR PFD
EUART_1
IB-bus
Parallel I/O Ports &
External Bus Port 0 Port 1Port 2 Port 3 Port4 Port 5
TWI
SPI
(2) (2) RESET T0 T1
(2) (2) P1 P2 P0 P3 INT0 INT1 P4 P5
(1) (1) (1)(1) SDA SCL MISO MOSI SCK SS
(1): Alternate function of Port 1 (2): Alternate function of Port 3 (3): Alternate function of Port 6
3
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Pin Configurations
P1.1/T2EX/SS
P1.4/CEX1
P1.3/CEX0
6 5 4 3 2 1 44 43 42 41 40 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEx4/MOSI RST P3.0/RxD_0 P6.0/RxD_1/SDA P3.1/TxD_0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA P6.1/TxD_1/SCL ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
P0.2/AD2 P0.3/AD3 35 34 33 32 31 30 29 P2.3/A11 P2.4/A12
P0.0/AD0 P2.1/A9
AT89C51RE2 PLCC44
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR Tx_OCD P2.0/A8 P2.2/A10 P3.7/RD XTAL2 XTAL1 VSS
P0.1/AD1
P1.2/ECI
Rx_OCD
P1.0/T2
VCC
P1.0/T2/XTALB1
P1.1/T2EX/SS
P1.4/CEX1
P1.3/CEX0
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 43 42 41 40 39 38 37 36 35 34 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI RST P3.0/RxD_0 P6.0/RxD_1/SDA P3.1/TxD_0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA P6.1/TxD_1/SCL ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
AT89C51RE2
P0.3/AD3 29 28 27 26 25 24 23
Rx_OCD
P1.2/ECI
VQFP44
12 13 14 15 16 17 18 19 20 21 22
P2.3/A11 P2.4/A12 XTAL1 P3.6/WR Tx_OCD P2.0/A8 P3.7/RD P2.2/A10 P2.1/A9 XTAL2 VSS
4
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VCC
AT89C51RE2
Table 2. Pin Description
Pin Number Mnemonic VSS Vss1 VCC P0.0-P0.7 44 43-36 LCC 22 VQFP 1.4 16 39 38 37-30 Type I I I I/O Name and Function Ground: 0V reference Optional Ground: Contact the Sales Office for ground connection. Power Supply: This is the power supply voltage for normal, idle and power-down operation Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for TSC8x54/58 Port 1 include: 2 3 4 5 6 7 8 9 P2.0-P2.7 24-31 40 41 42 43 44 1 2 3 18-25 I/O I I I/O I/O I/O I/O I/O I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control ECI (P1.2): External Clock for the PCA CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.5 for RB devices P2.0 to P2.6 for RC devices P2.0 to P2.7 for RD devices. P3.0-P3.7 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. RXD_0 (P3.0): Serial input port TXD_0 (P3.1): Serial output port INT0 (P3.2): External interrupt 0
P1.0-P1.7
2-9
40-44 1-3
I/O
11 13 14
5 7 8
I O I
5
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Pin Number Mnemonic LCC 15 16 17 18 19 VQFP 1.4 9 10 11 12 13 Type I I I O O Name and Function INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Port 6: Port 6 is an 2-bit bidirectional I/O port with internal pull-ups. Port 6 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 6 pins that are externally pulled low will source current because of the internal pull-ups. Port 6 also serves some special features as listed below. I I/O O RXD_1 (P6.0): Serial input port SDA (P6.0) : TWI Serial Data SDA is the bidirectional TWI data line. TXD_1 (P6.1) : Serial output port SCL ( P6.1) : TWI Serial Clock 34 28 I/O SCL output the serial clock to slave peripherals. SCL input the serial clock from master. Reset 10 4 I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR's AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier Tx_OCD: On chip debug Serial output port Rx_OCD: On chip debug Serial input port
P6.0-P6.1
12,34
6, 28
12 12 34
6 6 28
ALE/PROG
33
27
O (I)
PSEN
32
26
O
EA
35
29
I
XTAL1
21
15
I
XTAL2 Tx_OCD Rx_OCD
20 23 1
14 17 39
O O I
6
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SFR Mapping
The Special Function Registers (SFRs) of the AT89C51RE2 fall into the following categories: * * * * * * * * * * * * * * * C51 core registers: ACC, B, DPH, DPL, PSW, SP I/O port registers: P0, P1, P2, P3, P4, P5, P6 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR_0, SADEN_0, SBUF_0, SCON_0, SADDR_1, SADEN_1, SBUF_1, SCON_1, PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) Power and clock control registers: PCON, CKAL, CKCON0_1 Hardware Watchdog Timer registers: WDTRST, WDTPRG Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1 Keyboard Interface registers: KBE, KBF, KBLS 2-wire Interface registers: SSCON, SSCS, SSDAT, SSADR SPI registers: SPCON, SPSTR, SPDAT BRG (Baud Rate Generator) registers: BRL_0, BRL_1, BDRCON_0, BDRCON_1 Memory register: FCON, FSTA Clock Prescaler register: CKRL Others: AUXR, AUXR1, CKCON0, CKCON1, BMSEL
7
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Table 3. C51 Core SFRs
Mnemonic ACC B PSW SP DPL DPH Add E0h F0h D0h 81h 82h 83h Name Accumulator B Register Program Status Word Stack Pointer Data Pointer Low byte Data Pointer High byte CY AC F0 RS1 RS0 OV F1 P 7 6 5 4 3 2 1 0
Table 4. System Management SFRs
Mnemonic PCON AUXR AUXR1 CKRL BMSEL CKCON0 CKCON1 Add 87h 8Eh A2h 97h 92h 8Fh AFh Name Power Control Auxiliary Register 0 Auxiliary Register 1 Clock Reload Register Bank Memory Select Clock Control Register 0 Clock Control Register 1 7
SMOD1_0
6
SMOD0_0
5 M0 U2 MBO0 PCAX2 -
4 POF XRS2 -
3 GF1 XRS1 GF2 -
2 GF0 XRS0 0 FBS2 T1X2 -
1 PD EXTRA M FBS1 T0X2 SIX2_1
0 IDL AO DPS FBS0 X2 SPIX2
EES MBO2 TWIX2 -
SP9 MBO1 WDX2 -
SIX2_0 -
T2X2 -
Table 5. Interrupt SFRs
Mnemonic IEN0 IEN1 IPH0 IPL0 IPH1 IPL1 Add A8h B1h B7h B8h B3h B2h Name Interrupt Enable Control 0 Interrupt Enable Control 1 Interrupt Priority Control High 0 Interrupt Priority Control Low 0 Interrupt Priority Control High 1 Interrupt Priority Control Low 1 7 EA 6 EC PPCH PPCL 5 ET2 PT2H PT2L 4 ES PSH PSL 3 ET1 ES_1 PT1H PT1L PSH_1 PSL_1 2 EX1 ESPI PX1H PX1L SPIH SPIL 1 ET0 ETWI PT0H PT0L IE2CH IE2CL 0 EX0 EKBD PX0H PX0L KBDH KBDL
Table 6. Port SFRs
Mnemonic P0 P1 P2 P3 P4 Add 80h 90h A0h B0h C0h Name 8-bit Port 0 8-bit Port 1 8-bit Port 2 8-bit Port 3 8-bit Port 4 7 6 5 4 3 2 1 0
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Table 6. Port SFRs
Mnemonic P5 P6 Add E8h F8h Name 8-bit Port 5 2-bit Port 5 7 6 5 4 3 2 1 0
Table 7. Flash and EEPROM Data Memory SFR
Mnemonic FCON FSTA Add D1h D3h Name Flash Controller Control Flash Controller Status 7 FPL3 FMR 6 FPL2 5 FPL1 4 FPL0 3 FPS 2 FMOD2 FSE 1 FMOD1 FLOAD 0 FMOD0 FBUSY
Table 8. Timer SFRs
Mnemonic TCON TMOD TL0 TH0 TL1 TH1 WDTRST WDTPRG T2CON T2MOD RCAP2H Add 88h 89h 8Ah 8Ch 8Bh 8Dh A6h A7h C8h C9h CBh Name Timer/Counter 0 and 1 Control Timer/Counter 0 and 1 Modes Timer/Counter 0 Low Byte Timer/Counter 0 High Byte Timer/Counter 1 Low Byte Timer/Counter 1 High Byte WatchDog Timer Reset WatchDog Timer Program Timer/Counter 2 control Timer/Counter 2 Mode Timer/Counter 2 Reload/Capture High byte Timer/Counter 2 Reload/Capture Low byte Timer/Counter 2 High Byte Timer/Counter 2 Low Byte TF2 EXF2 RCLK TCLK EXEN2 WTO2 TR2 WTO1 C/T2# T2OE WTO0 CP/RL2# DCEN 7 TF1 GATE1 6 TR1 C/T1# 5 TF0 M11 4 TR0 M01 3 IE1 GATE0 2 IT1 C/T0# 1 IE0 M10 0 IT0 M00
RCAP2L TH2 TL2
CAh CDh CCh
Table 9. PCA SFRs
Mnemo -nic CCON CMOD CL Add Name D8h D9h E9h PCA Timer/Counter Control PCA Timer/Counter Mode PCA Timer/Counter Low byte 7 CF CIDL 6 CR WDTE 5 4 CCF4 3 CCF3 2 CCF2 CPS1 1 CCF1 CPS0 0 CCF0 ECF
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Table 9. PCA SFRs (Continued)
Mnemo -nic CH Add Name F9h PCA Timer/Counter High byte ECOM0 ECOM1 ECOM2 ECOM3 ECOM4 CAPP0 CAPP1 CAPP2 CAPP3 CAPP4 CAPN0 CAPN1 CAPN2 CAPN3 CAPN4 MAT0 MAT1 MAT2 MAT3 MAT4 TOG0 TOG1 TOG2 TOG3 TOG4 PWM0 PWM1 PWM2 PWM3 PWM4 ECCF0 ECCF1 ECCF2 ECCF3 ECCF4 7 6 5 4 3 2 1 0
CCAPM0 DAh PCA Timer/Counter Mode 0 CCAPM1 DBh PCA Timer/Counter Mode 1 CCAPM2 DCh PCA Timer/Counter Mode 2 CCAPM3 DDh PCA Timer/Counter Mode 3 CCAPM4 DEh PCA Timer/Counter Mode 4 CCAP0H FAh CCAP1H FBh
PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0 PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0
CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0 CCAP3H FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0 CCAP4H FEh CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0 CCAP0L6 CCAP1L6 CCAP2L6 CCAP3L6 CCAP4L6 CCAP0L5 CCAP0L4 CCAP1L5 CCAP1L4 CCAP2L5 CCAP2L4 CCAP3L5 CCAP3L4 CCAP4L5 CCAP4L4 CCAP0L3 CCAP0L2 CCAP1L3 CCAP1L2 CCAP2L3 CCAP2L2 CCAP3L3 CCAP3L2 CCAP4L3 CCAP4L2 CCAP0L1 CCAP1L1 CCAP2L1 CCAP3L1 CCAP4L1 CCAP0L0 CCAP1L0 CCAP2L0 CCAP3L0 CCAP4L0
EAh PCA Compare Capture Module 0 L CCAP0L7 EBh PCA Compare Capture Module 1 L CCAP1L7 ECh PCA Compare Capture Module 2 L CCAP2L7 EDh PCA Compare Capture Module 3 L CCAP3L7 EEh PCA Compare Capture Module 4 L CCAP4L7
Table 10. Serial I/O Port SFRs
Mnemonic SCON_0 SBUF_0 SADEN_0 SADDR_0 BDRCON_0 BRL_0 SCON_1 SBUF_1 SADEN_1 SADDR_1 BDRCON_1 BRL_1 Add 98h 99h B9h A9h 9Bh 9Ah C0h C1h BAh AAh BCh BBh Name Serial Control 0 Serial Data Buffer 0 Slave Address Mask 0 Slave Address 0 Baud Rate Control 0 Baud Rate Reload 0 Serial Control 1 Serial Data Buffer 1 Slave Address Mask 1 Slave Address 1 Baud Rate Control 1 Baud Rate Reload 1 SMOD1_1 SMOD0_1 BRR_1 TBCK_1 RBCK_1 SPD_1 SRC_1 FE_1/SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 BRR_0 TBCK_0 RBCK_0 SPD_0 SRC_0 7 FE/SM0_0 6 SM1_0 5 SM2_0 4 REN_0 3 TB8_0 2 RB8_0 1 TI_0 0 RI_0
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Table 11. SPI Controller SFRs
Mnemonic SPCON SPSCR SPDAT Add C3h C4h C5h Name SPI Control SPI Status SPI Data 7 SPR2 SPIF SPD7 SPD6 6 SPEN 5 SSDIS OVR SPD5 4 MSTR MODF SPD4 3 CPOL SPTE SPD3 2 CPHA UARTM SPD2 1 SPR1 SPTEIE SPD1 0 SPR0 MODFIE SPD0
Table 12. Two-Wire Interface Controller SFRs
Mnemonic SSCON SSCS SSDAT SSADR Add 93h 94h 95h 96h Name Synchronous Serial control Synchronous Serial Status Synchronous Serial Data Synchronous Serial Address 7 SSCR2 SSC4 SSD7 SSA7 6 SSPE SSC3 SSD6 SSA6 5 SSSTA SSC2 SSD5 SSA5 4 SSSTO SSC1 SSD4 SSA4 3 SSI SSC0 SSD3 SSA3 2 SSAA 0 SSD2 SSA2 1 SSCR1 0 SSD1 SSA1 0 SSCR0 0 SSD0 SSGC
Table 13. Keyboard Interface SFRs
Mnemonic KBLS KBE KBF Add 9Ch 9Dh 9Eh Name Keyboard Level Selector Keyboard Input Enable Keyboard Flag Register 7 KBLS7 KBE7 KBF7 6 KBLS6 KBE6 KBF6 5 KBLS5 KBE5 KBF5 4 KBLS4 KBE4 KBF4 3 KBLS3 KBE3 KBF3 2 KBLS2 KBE2 KBF2 1 KBLS1 KBE1 KBF1 0 KBLS0 KBE0 KBF0
11
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Table below shows all SFRs with their address and their reset value. Table 14. SFR Mapping
Bit addressable 0/8 F8h P6 XXXX XX11 B 0000 0000 P5 1111 1111 ACC 0000 0000 CCON 00X0 0000 PSW 0000 0000 T2CON 0000 0000 SCON_1 0000 0000 P4 1111 1111 IPL0 X000 000 P3 1111 1111 IEN0 0000 0000 P2 1111 1111 SCON_0 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 TMOD 0000 0000 SP 0000 0111 1/9 SBUF_0 XXXX XXXX SADEN_0 0000 0000 IEN1 XXXX 0000 SADDR_0 0000 0000 SADEN1 0000 0000 IPL1 XXXX 0000 SADDR_1 0000 0000 AUXR1 000x 11x0 BRL_0 0000 0000 BMSEL 0000 0YYY TL0 0000 0000 DPL 0000 0000 2/A BDRCON_0 XXX0 0000 SSCON 0000 0000 TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E KBLS 0000 0000 SSCS 1111 1000 TH0 0000 0000 KBE 0000 0000 SSDAT 1111 1111 TH1 0000 0000 WDTRST XXXX XXXX KBF 0000 0000 SSADR 1111 1110 AUXR XX00 1000 CKRL 1111 1111 CKCON0 0000 0000 PCON 00X1 0000 7/F BRL_1 0000 0000 IPH1 XXXX 0111 BDRCON_1 XXX0 0000 IPH0 X000 0000 CKCON1 XXXX XX00 WDTPRG XXXX X000 BFh SBUF_1 0000 0000 SPCON 0001 0100 SPSCR 0000 0000 SPDAT XXXX XXXX C7h CMOD 00XX X000 FCON 0000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 CCAPM0 X000 0000 CCAPM1 X000 0000 FSTA xxxx x000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CCAPM2 X000 0000 CCAPM3 X000 0000 CCAPM4 X000 0000 CL 0000 0000 CCAP0L XXXX XXXX CCAP1L XXXX XXXX CCAP2L XXXX XXXX CCAP3L XXXX XXXX CCAP4L XXXX XXXX 1/9 CH 0000 0000 2/A CCAP0H XXXX XXXX 3/B CCAP1H XXXX XXXX Non Bit addressable 4/C CCAP2H XXXX XXXX 5/D CCAP3H XXXX XXXX 6/E CCAP4H XXXX XXXX 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h
D8h
DFh
D0h
D7h
C8h U2(AUXR1.5) =0 C0h U2(AUXR1.5) =1 B8h
CFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
Reserved
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AT89C51RE2
Enhanced Features
In comparison to the original 80C52, the AT89C51RE2 implements some new features, which are: * * * * * * * * * * * * X2 option Dual Data Pointer Extended RAM Extended stack Programmable Counter Array (PCA) Hardware Watchdog SPI interface 4-level interrupt priority system power-off flag ONCE mode ALE disabling Enhanced features on the UART and the timer 2
X2 Feature
The AT89C51RE2 core needs only 6 clock periods per machine cycle. This feature called `X2' provides the following advantages: * * * * Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Save power consumption while keeping same CPU power (oscillator power saving). Save power consumption by dividing dynamically the operating frequency by 2 in operating and idle modes. Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. Description The clock for the whole circuit and peripherals is first divided by two before being used by the CPU core and the peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 2 shows the clock generation block diagram. X2 bit is validated on the rising edge of the XTAL1/2 to avoid glitches when switching from X2 to STD mode. Figure 3 shows the switching mode waveforms. Figure 2. Clock Generation Diagram
CKRL XTAL1 FXTAL 2 XTAL1:2 0 1 FOSC 8 bit Prescaler FCLK CPU FCLK PERIPH
X2 CKCON0
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Figure 3. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 bit
CPU clock STD Mode
FOSC X2 Mode STD Mode
The X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of the Fuse Configuration Byte (FCB). By default, Standard mode is active. Setting the X2 bit activates the X2 feature (X2 mode). The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (See Table 15.) and SPIX2 bit in the CKCON1 register (see Table 16) allows a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode.
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Table 15. CKCON0 Register CKCON0 - Clock Control Register (8Fh)
7 TWIX2 Bit Number 6 WDX2 Bit Mnemonic Description 2-wire cloTBck (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no 7 TWIX2 effect) Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Watchdog Clock 6 WDX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array Clock 5 PCAX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART0 Clock (Mode 0 and 2) 4 SIX2_0 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer2 Clock 3 T2X2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer1 Clock 2 T1X2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer0 Clock 1 T0X2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU Clock 0 X2 Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals'X2' bits. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is cleared. 5 PCAX2 4 SIX2_0 3 T2X2 2 T1X2 1 T0X2 0 X2
Reset Value = X000 000'HSB. X2'b (See "Fuse Configuration Byte: FCB") Not bit addressable
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Table 16. CKCON1 Register CKCON1 - Clock Control Register (AFh)
7 Bit Number 7 6 5 4 3 2 6 Bit Mnemonic Description Reserved Reserved Reserved Reserved Reserved Reserved Enhanced UART1 Clock (Mode 0 and 2) 1 SIX2_1 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 4 3 2 1 SIX2_1 0 SPIX2
0
SPIX2
Reset Value = XXXX XX00b Not bit addressable
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Dual Data Pointer Register DPTR
The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 17) that allows the program code to switch between them (Refer to Figure 4).
Figure 4. Use of Dual Pointer
External Data Memory
7
0 DPS
DPTR1 DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)
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Table 17. AUXR1 register AUXR1- Auxiliary Register 1(0A2h)
7 EES Bit Number 6 SP9 Bit Mnemonic Description Enable Extended Stack This bit allows the selection of the stack extended mode. Set to enable the extended stack Clear to disable the extended stack (default value) Stack Pointer 9th Bit This bit has no effect when the EES bit is cleared. Set when the stack pointer belongs to the XRAM memory space Cleared when the stack pointer belongs to the 256bytes of internal RAM. P4 bit addressable 5 U2 Clear to map SCON_1 register at C0h sfr address Set to map P4 port register at C0h address. 4 3 2 1 GF2 0 Reserved The value read from this bit is indeterminate. Do not set this bit. This bit is a general purpose user flag. * Always cleared. Reserved The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection Cleared to select DPTR0. Set to select DPTR1. 5 U2 4 3 GF2 2 0 1 0 DPS
7
EES
6
SP9
0
DPS
Reset Value: XX0X XX0X0b Not bit addressable
Note: *Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address
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0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
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Memory Architecture
AT89C51RE2 features several on-chip memories: * * * Physical memory organisation Figure 5. Physical memory organisation
Fuse Configuration Byte(1 byte) Hardware Security (1 byte) Column Latches (128 bytes) 1FFFFh FCB HSB
Flash memory: containing 128 Kbytes of program memory (user space) organized into 128 bytes pages. Boot ROM: 4K bytes for boot loader. 8K bytes internal XRAM
128K bytes Flash memory user space FM0
4K bytes ROM RM0
8K bytes XRAM
00000h
256 bytes IRAM
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Expanded RAM (XRAM)
The AT89C51RE2 provides additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage. AT89C51RE2 devices have expanded RAM in external data space configurable up to 8192bytes (see Table 18.). The AT89C51RE2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable only. 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register (see Table 18). The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space.
Figure 6. Internal and External Data Memory Address
0FFh to 1FFFh 0FFh Upper 128 bytes Internal Ram indirect accesses XRAM 80h 7Fh Lower 128 bytes Internal Ram direct or indirect accesses 00 00 80h 0FFh 0FFFFh
Special Function Register direct accesses
External Data Memory
00FFh up to 1FFFh 0000
When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. * * Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h). The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table 18. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM.
*
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* With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the use of DPTR. With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD).
*
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may be located in the 256 lower bytes of the XRAM by activating the extended stack mode (see EES bit in AUXR1). The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals.
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Registers
Table 18. AUXR Register AUXR - Auxiliary Register (8Eh)
7 6 5 M0 4 XRS2 3 XRS1 2 XRS0 1 EXTRAM 0 AO
Bit Number 7
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Pulse length
6
-
5
M0
Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock periods. XRAM Size XRS2 XRS1 XRS0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 1 1 XRAM size 256 bytes 512 bytes 768 bytes 1024 bytes 1792 bytes 2048 bytes 4096 bytes 8192 bytes (default)
4-2
XRS2:0
EXTRAM bit Cleared to access internal XRAM using movx @ Ri/ @ DPTR. 1 EXTRAM Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used.
0
AO
Reset Value = XX01 1100b Not bit addressable
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Extended Stack
The lowest bytes of the XRAM may be used to allow extension of the stack pointer. The extended stack allows to extend the standard C51 stack over the 256 bytes of internal RAM. When the extended stack mode is activated (EES bit in AUXR1), the stack pointer (SP) can grow in the lower 256 bytes of the XRAM area. The stack extension consists in a 9 bits stack pointer where the ninth bit is located in SP9 (bit 6 of AUXR1). The SP9 then indicates if the stack pointer belongs to the internal RAM (SP9 cleared) or to the XRAM memory (SP9 set). To ensure backward compatibility with standard C51 architecture, the extended mode is disable at chip reset. Figure 7. Stack modes
Logical MCU Address FFFFh Logical MCU Address FFFFh
SP Value
SP Value
XRAM
XRAM
00FFh
FFh SP9=1
0000h FFh FFh
0000h FFh 256 SP values rollover within 256B of IRAM
00h FFh
256 bytes IRAM
00h 00h
256 bytes IRAM
00h 00h
SP9=0
512 SP Values rollover in: 256B of IRAM + lower 256B of XRAM
Standard C51 Stack mode EES = 0
Extended Stack mode Stack EES = 1
Figure 8. AUXR1 register AUXR1- Auxiliary Register 1(0A2h)
7 EES Bit Number 6 SP9 Bit Mnemonic Description Enable Extended Stack This bit allows the selection of the stack extended mode. Set to enable the extended stack Clear to disable the extended stack (default value) 5 U2 4 3 GF2 2 0 1 0 DPS
7
EES
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Bit Number
Bit Mnemonic Description Stack Pointer 9th Bit This bit has no effect when the EES bit is cleared.
6
SP9
Set when the stack pointer belongs to the XRAM memory space Cleared when the stack pointer belongs to the 256bytes of internal RAM. Set and cleared by hardware. Can only be read. P4 bit addressable
5
U2
Clear to map SCON_1 register at C0h sfr address Set to map P4 port register at C0h address.
4 3 2 1
GF2 0 -
Reserved The value read from this bit is indeterminate. Do not set this bit. This bit is a general purpose user flag. * Always cleared. Reserved The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection Cleared to select DPTR0. Set to select DPTR1.
0
DPS
Reset Value = 00XX 00X0b Not bit addressable
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Flash Memory
General Description
The Flash memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 128K bytes of program memory organized in 1024 pages of 128 bytes. This memory is both parallel and serial In-System Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash. The programming does not require external high programming voltage. The necessary high programming voltage is generated on-chip using the standard VCC pins of the microcontroller.
Features
* * * * *
Flash internal program memory. Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space. This configuration provides flexibility to the user. Default loader in Boot Flash allows programming via the serial port without the need of a user provided loader. Up to 64K byte external program memory if the internal program memory is disabled (EA = 0). Programming and erase voltage with standard 5V or 3V VCC supply.
Flash memory organization
AT89C51RE2 features several on-chip memories: * * * Flash memory FM0: containing 128 Kbytes of program memory (user space) organized into 128 bytes pages. Boot ROM RM0: 4K bytes for boot loader. 8K bytes internal XRAM
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Physical memory organisation
Figure 9. Physical memory organisation
Fuse Configuration Byte(1 byte) Hardware Security (1 byte) Extra Row FM0 (128 bytes) Column Latches (128 bytes) 1FFFFh FCB HSB
4K bytes ROM RM0 128K bytes Flash memory user space FM0
00000h
On-Chip Flash memory
The AT89C51RE2 implements up to 128K bytes of on-chip program/code memory. Figure 9 and Figure 10 shows the partitioning of internal and external program/code memory spaces according to EA value. The memory partitioning of the 8051 core microcontroller is typical a Harvard architecture where program and data areas are held in separate memory areas. The program and data memory areas use the same physical address range from 0000H-FFFFH and a 8 bit instruction code/data format. To access more than 64kBytes of code memory, without modifications of the MCU core, and development tools, the bank switching method is used. The internal program memory is expanded to 128kByte in the Expanded Configuration', the data memory remains in the Normal Configuration. The program memory is split into four 32 kByte banks (named Bank 0-2). The MCU core still addresses up to 64kBytes where the upper 32Kbytes can be selected between 3 32K bytes bank of on-chip flash memory. The lower 32K bank is used as common area for interrupt subroutines, bank switching and functions calls between banks. The AT89C51RE2 also implements an extra upper 32K bank (Bank3) that allows external code execution.
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Figure 10. Program/Code Memory Organization EA=1
Logical MCU Address FFFFh Physical Flash Address 0FFFFh Logical MCU Address FFFFh Physical Flash Address 17FFFh Logical MCU Address FFFFh Physical Flash Address 1FFFFh Logical MCU Address FFFFh
upper 32K Bank 0
upper 32K Bank 1
upper 32K Bank 2
upper 32K Bank 3 Optional External Memory
18000h 8000h
8000h 7FFFh
08000h 07FFFh
8000h
10000h
8000h
32K Common On-Chip flash code memory
0000h 00000h
External code memory
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When EA=0, the on-chip flash memory is disabled and the MCU core can address only up to 64kByte of external memory (none of the on-chip flash memory FM0 banks or RM0 can be mapped and executed). Figure 11. Program/Code Memory Organization EA=0
Logical MCU Address FFFFh External Physical Memory Address 0FFFFh
64K Common
On-Chip flash code memory
0000h 00000h
External code memory
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On-Chip ROM bootloader
The On-chip ROM bootloader (RM0) is enable only for ISP operations after reset (bootloader execution). The RM0 memory area belongs to a logical addressable memory space called `Bank Boot'. RM0 cannot be activated from the On-chip flash memory. It means that it is not possible activate the Bank Boot area by software (it prevents any RM0 execution and flash corruption from the user application). RM0 logical area consists in an independent code execution memory area of 4K bytes starting at logical 0x0000 address (it allows the use of the interrupts in the bootloader execution).
Logical MCU Address FFFFh
Physical Address 0FFFFh
Logical MCU Address FFFFh
Physical Address 17FFFh
Logical MCU Address FFFFh
Physical Address 1FFFFh
Logical MCU Address FFFFh
Bank 0
Bank 1
Bank 2
Bank 3 (Ext)
18000h 8000h
8000h 7FFFh
08000h 07FFFh
8000h
10000h
8000h
Logical MCU Address
ROM Address 1000h
On-Chip ROM memory (RM0) On-Chip flash code memory External code memory
0000h 00000h
1000h
0000h
Bank BOOT
0000h
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Boot process
The BRV2-0 bits of the FCB (see Table 20 on page 34), the EA pin value upon reset and the presence of the external hardware conditions, allow to modify the default reset vector of the AT89C51RE2. The Hardware conditions (EA = 1, PSEN = 0) during the Reset falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user's code but can be manually forced into default ISP operation. The hardware conditions allows to force the enter in ISP mode whatever the configurations bits.
Figure 12. Boot Reset vector configuration
EA pin 0 Hardware conditions X YES BRV2-0 X X 111 110 101 1 NO 011 010 001 000 Reserved (FM0 at address 0x0000 with bank 0 mapped) RM0 at address 0x0000 (ATMEL Bootloader) 100 MCU reset vector External Code at address 0x0000 RM0 at address 0x0000 (ATMEL Bootloader) FM0 at address 0x0000 with bank0 mapped FM0 at address 0xFFFC in Bank 0 FM0 at address 0xFFFC in Bank 1 FM0 at address 0xFFFC in Bank 2
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FM0 Memory Architecture The FM0 flash memory is made up of 5 blocks: 1. The memory array (user space) 128K bytes 2. The Extra Row also called FM0 XAF 3. The Hardware security bits (HSB) 4. The Fuse Configuration Byte (FCB) 5. The column latch User Space This space is composed of a 128K bytes Flash memory organized in 1024 pages of 128 bytes. It contains the user's application code. This block can be access in Read/write mode from FM0 and boot memory area. (When access in write mode from FM0, the CPU core enter pseudo idle mode). This row is a part of FM0 and has a size of 128 bytes. The extra row (XAF) may contain information for boot loader usage.This block can be access in Read/write mode from FM0 and boot memory area. (When access in write mode from FM0, the CPU core enter pseudo idle mode).
Extra Row (XRow or XAF)
Hardware security Byte (HSB)
The Hardware security Byte is a part of FM0 and has a size of 1 byte. The 8 bits can be read/written by software (from FM0 or RM0) and written by hardware in parallel mode. The HSB bits can be written to `0' without any restriction (increase the security level of the chip), but can be written to `1' only when the corresponding memory area of the lock bits was full chip erased. Table 19. Hardware Security Byte (HSB)
7 Bit Number 7 6-4 3 2-0 6 Bit Mnemonic FLB2-0 5 4 3 2 FLB2 1 FLB1 0 FLB0
Description Unused Reserved Unused FM0 Memory Lock Bits See Table 32 on page 52
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Fuse Configuration Byte (FCB)
The Fuse configuration byte is a part of FM0. The 8 bits read/written by software (from FM0 or RM0) and written by hardware in parallel mode. Table 20. Fuse Configuration Byte (FCB)
7 X2 Bit Number 6 Bit Mnemonic 5 4 3 2 BRV2 1 BRV1 0 BRV0
Description X2 Mode Programmed (`0' value) to force X2 mode (6 clocks per instruction) after reset Unprogrammed (`1' value) to force X1 mode, Standard Mode, after reset (Default)
7
X2
6-3
-
Unused Boot Reset Vector These bits allow to configure the reset vector of the product according to the following values: 1 1 1: Reset at address 0x0000 of FM0 with Bank0 mapped 1 1 0: Reset at address 0xFFFC of Bank 0
2-0
BRV2-0-
1 0 1: Reset at address 0xFFFC of Bank 1 1 0 0: Reset at address 0xFFFC of Bank 2 0 1 1: Reset at address 0x0000 of RM0 (Internal ROM bootloader execution) 0 1 0: Reserved for further extension but same as 1 1 1 0 0 1: Reserved for further extension but same as 1 1 1 0 0 0: Reserved for further extension but same as 1 1 1
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Column latches The column latches, also part of FM0, has a size of one page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW, Hardware security byte and Fuse Configuration Byte). This block is write only from FM0, RM0.
Cross Memory Access Description overview
The FM0 memory can be programmed from RM0 without entering idle mode. Programming FM0 from FM0 makes the CPU core entering "pseudo idle" mode. In the pseudo idle mode, the code execution is halted, the peripherals are still running (like standard idle mode) but all interrupt are delayed to the end of this mode. There are fours ways of exiting pseudo idle mode: * * * * At the end of the regular flash programming operation Reset the chip by external reset Reset the chip by hardware watchdog Reset the chip by PCA watchdog
Programming FM0 from external memory code (EA=0 or EA=1,with Bank3 active) is impossible. If a reset occurs during flash programming the target page could be incompletely erased or programmed, but any other memory location (FM0, RAM, XRAM) remain unchanged. The Table 21 shows all software flash access allowed. Table 21. Cross Memory Access
Action Read Code executing from FM0 (user Flash) Load column latch Write Read RM0 (boot ROM) Load column latch Write External memory EA = 0 or EA=1, Bank3 Read Load column latch Write FM0 (user Flash) ok ok ok (pseudo idle mode) ok ok ok
(1)
RM0 (boot ROM) Denied N.A. N.A. ok N.A. N.A. Denied N.A. N.A.
Denied Denied
1.
Depends of general lock bits configuration
N.A. Not applicable
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Access and Operations Descriptions
FM0 FLASH Registers The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the columns latch, HSB, FCB and extra row in the working data or code space. BMSEL Register Table 22. BMSEL Register BMSEL Register (S:92h) Bank Memory Select
7 MBO2 6 MBO1 Bit Mnemonic 5 MBO0 4 3 2 FBS2 1 FBS1 0 FBS0
Bit Number
Description Memory Bank Operation These bits select the target memory bank for flash write or read operation. These bits allows to read or write the on-chip flash memory from one upper 32K bytes to another one.
7-5
MBO2:0
0 X X: The on-chip flash operation target banked is the same as FBS2:0 1 0 0: The target memory bank is forced to Bank0 1 0 1: The target memory bank is forced to Bank1 1 1 0: The target memory bank is forced to Bank2 1 1 1: The target memory bank is forced to Bank3 (optional External bank)
4-3
Reserved Fetch Bank Selection These bits select the upper 32K bytes execution bank: FBS1:0 can be read/write by software. FBS2 is read-only by software (the Boot bank can not be mapped from FM0) 0 0 0 Bank0 0 0 1 Bank1 0 1 0 Bank2 0 1 1 Bank3 (optionnal external bank) 1 X X Boot Bank (Read only) Upon reset FBS2:0 is initialized according to BRV2:0 configuration bits in FCB.
2-0
FBS2:0
Reset Value= 0000 0YYYb (where YYY depends on BRV2:0 value in Fuse Configuration Byte)
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FCON Register Table 23. FCON Register FCON Register (S:D1h) Flash Control Register
7 FPL3 6 FPL2 Bit Mnemonic 5 FPL1 4 FPL0 3 FPS 2 FMOD2 1 FMOD1 0 FMOD0
Bit Number
Description Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD2:0. (see Table 26.) Flash Map Program Space When this bit is set:
7-4
FPL3:0
3
FPS
The MOVX @DPTR, A instruction writes in the columns latches space When this bit is cleared: The MOVX @DPTR, A instruction writes in the regular XDATA memory space Flash Mode These bits allow to select the target memory area and operation on FM0 See Table 25.
2-0
FMOD2:0
Reset Value= 0000 0000b
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FSTA Register Table 24. FSTA Register FSTA Register (S:D3h) Flash Status Register
7 FMR 6 Bit Mnemonic 5 4 3 2 FSE 1 FLOAD 0 FBUSY
Bit Number
Description Flash Movc Redirection When code is executed from RM0 (and only RM0), this bit allow the MOVC instruction to be redirected to FM0. Clear this bit to allow MOVC instruction to read FM0 Set this bit to allow MOVC instruction to read RM0 This bit can be written only from RM0 (on-chip ROM bootloader execution).
7
FMR
6-3
-
unused Flash sequence error Set by hardware when the flash activation sequencers FCON 5X and MOV FCON AX) is not correct (See Error Report Section) Clear by software or clear by hardware if the last activation sequence was correct (previous error is canceled) Flash Columns latch loaded Set by hardware when the first data is loaded in the column latches. Clear by hardware when the activation sequence succeeds (flash write success, or reset column latch success) Flash Busy Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.
2
FSE
1
FLOAD
0
FBUSY
Reset Value= `R'xxx x000b Where `R' depends on the reset conditions: If RM0 is executed after Reset R=1, if FM0 is executed after reset R=0
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Mapping of the Memory Space
By default, the user space is accessed by MOVC A, @A+DPTR instruction for read only. Setting FPS bit in FCON register takes precedence on the EXTRAM bit in AUXR register. The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD2:0 in FCON register in accordance with Table 25. A MOVC instruction is then used for reading these spaces. Thanks to the columns latches access, it is possible to write FM0 array, HSB and extra row blocks. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to FFFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Table 25. .FM0 blocks select bits
FMOD2 0 0 0 0 1 1 1 1 FMOD1 0 0 1 1 0 0 1 1 FMOD0 0 1 0 1 0 1 0 Reserved 1 Adressable Space FM0 array(0000h-FFFFh) Extra Row(00h-80h) Erase FM0 Column latches reset HSB FCB
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Launching flash commands (activation sequence)
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the operation. This sequence is 5xh followed by Axh. Table 26 summarizes the memory spaces to program according to FMOD2:0 bits. Table 26. FM0 Programming Sequences
Write to FCON FPL3:0 5 FM0 A 5 XAF FM0 A 5 Erase FM0 A Reset FM0 Column Latches 5 A 5 HSB A 5 FCB A 5 Reserved A 5 Reserved A X 1 1 1 X X 1 1 1 1 0 No action 1 X X 1 1 0 1 1 0 X X 1 1 0 0 0 1 X X X X 0 0 0 1 1 1 1 0 0 1 1 0 Full erase FM0 memory area No action Reset the FM0 column latches No action Write the hardware Security byte (HSB) See (4) No action Write the Fuse Configuration Byte (FCB) X X 0 0 0 1 1 0 Write the column latches in FM0 extra row space No action X X 0 0 0 0 0 1 Write the column latches in FM0 No action FPS X FMOD2 0 FMOD1 0 FMOD0 0 Operation No action
Note:
1. The sequence 5xh and Axh must be executed without instructions between them otherwise the programming is not executed (see flash status register). 2. The sequence 5xh and Axh can be executed with the different FMOD0, FMOD1 values, the last FMOD1:0 value latches the destination target. 3. When the FMOD2 bit is set (corresponding to the serial number field code) no write operation can be performed. 4. Only the bits corresponding to the previously "full erase" memory space can be written to one.
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Loading the Column Latches
Any number of data from 0 byte to 128 bytes can be loaded in the column latches. The data written in the column latches can be written in a none consecutive order. The DPTR allows to select the address of the byte to load in the column latches. The page address to be written (target page in FM0) is given by the last address loaded in the column latches and when this page belongs to the upper 32K bytes of the logical addressable MCU space, the target memory bank selection is performed upon the MBO2:0 value during the last address loaded. When 0 byte is loaded in the column latches the activation sequence (5xh, Axh in FCON) does not launch any operations. The FSE bit in FSTA register is set. When a current flash write operation is on-going (FBUSY is set), it is impossible to load the columns latches before the end of flash programming process (the write operation in the columns latches is not performed, and the previous columns latches content is not overwritten). When programming is launched, an automatic erase of the entire memory page is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. The unloaded data of the target memory page are programmed at 0xFF value (automatic page erase value). The following procedure is used to load the column latches and is summarized in Figure 13: * * * * * * * * * Disable interrupt and map the column latch space by setting FPS bit. Select the target memory bank (for page address larger than 32K) Map the column latch Reset the column latch Load the DPTR with the address to write. Load Accumulator register with the data to write. Execute the MOVX @DPTR, A instruction, and only this one (no MOVX @Ri, A). If needed loop the last three instructions until the page is completely loaded. Unmap the column latch if needed (it can be left mapped) and Enable Interrupt
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Figure 13. Column Latches Loading Procedure
Column Latches Loading
Save & Disable IT EA= 0
Select target bank MB2:0=YY
Column Latches Reset FCON= 53h (FPS=0) FCON= ABh (FPS=1)
Data Load DPTR= Address ACC= Data Exec: MOVX @DPTR, A
Last Byte to load?
Data memory Mapping FCON = 00h (FPS = 0)
Restore IT and default target memory bank
Note: Note: Note:
The last page address used when loading the column latch is the one used to select the page programming address. The value of MB02:0 during the last load gives the upper 32K bytes bank target selection. The execution of this sequence when BUSY flag is set leads to the no-execution of the write in the column latches (the previous loaded data remains unchanged).
Writing the Flash Spaces User The following procedure is used to program the User space and is summarized in Figure 14: * * * Load up to one page of data in the column latches from address 0000h to FFFFh (see Figure 13.). Disable the interrupts. Launch the programming by writing the data sequence 50h followed by A0h in FCON register. The end of the programming indicated by the FBUSY flag cleared. Enable the interrupts.
*
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Extra Row The following procedure is used to program the Extra Row space and is summarized in Figure 14: * * * Load data in the column latches from address FF80h to FFFFh. Disable the interrupts. Launch the programming by writing the data sequence 51h followed by A1h in FCON register. The end of the programming indicated by the FBUSY flag cleared. Enable the interrupts.
*
Figure 14. Flash and Extra row Programming Procedure
Flash Programming
XROW Programming
Column Latches Loading see Figure 13
Column Latches Loading see Figure 13
Save & Disable IT EA= 0
Save & Disable IT EA= 0
Launch Programming FCON= 50h FCON= A0h
Launch Programming FCON= 51h FCON= A1h
FBusy Cleared?
FBusy Cleared?
Clear Mode FCON = 00h
Clear Mode FCON = 00h
End Programming Restore IT
End Programming Restore IT
Hardware Security Byte (HSB)
The following procedure is used to program the Hardware Security Byte space and is summarized in Figure 15:
* * * * * Set FPS and map Hardware byte (FCON = 0x0C) Save and disable the interrupts. Load DPTR at address 0000h Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction.
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*
Launch the programming by writing the data sequence 54h followed by A4h in FCON register. The end of the programming indicated by the FBusy flag cleared. Restore the interrupts
* .
Figure 15. Hardware Security Byte Programming Procedure
HSB Programming
Save & Disable IT EA= 0
FCON = 0Ch
Data Load DPTR= 00h ACC= Data Exec: MOVX @DPTR, A
Launch Programming FCON= 54h FCON= A4h
FBusy Cleared?
Clear Mode FCON = 00h
End Programming RestoreIT
Fuse Configuration Byte (FCB)
The following procedure is used to program the Fuse Configuration Byte space and is summarized in Figure 16:
* * * * * Set FPS and map FCB (FCON = 0x0D) Save and disable the interrupts. Load DPTR at address 0000h Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction.
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* Launch the programming by writing the data sequence 55h followed by A5h in FCON register. The end of the programming indicated by the FBusy flag cleared. Restore the interrupts
* .
Figure 16. Fuse Configuration Byte Programming Procedure
FCB Programming
Save & Disable IT EA= 0
FCON = 0Dh
Data Load DPTR= 00h ACC= Data Exec: MOVX @DPTR, A
Launch Programming FCON= 55h FCON= A5h
FBusy Cleared?
Clear Mode FCON = 00h
End Programming RestoreIT
Reset of columns latches space
No automatic reset of the columns latches is performed after a successful flash write process. Resetting the columns latches during a flash write process is mandatory. User shall implement a reset of the column latch before each column latch load sequence.
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In addition, the user application can reset the columns latches space manually. The following procedure is used to reset the columns latches space Launch the programming by writing the data sequence 53h followed by A3h in FCON register (from FM0 and RM0).
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Errors Report / Miscellaneous states Flash Busy flag The FBUSY flag indicates on-going flash write operation. The busy flag is set by hardware, the hardware clears this flag after the end of the programming operation. Flash Programming Sequence Error When a wrong sequence is detected the FSE in FSTA is set. The following events are considered as not correct activation sequence: - The two "MOV FCON,5x and MOV FCON, Ax" were not consecutive, or the second instruction differs from "MOV FCON Ax" (for example, an interrupt occurs during the sequence). - The sequence (write flash or reset column latches) occurred with no data loaded in the column latches The FSE bit can be cleared: - By software - By hardware when a correct programming sequence occurs. Note: When a good sequence occurs just after an incorrect sequence, the previous error is lost. The user software application should take care to check the FSE bit before initiating a new sequence. Power Down Mode Request
In Power Down mode, the on-chip flash memory is deselected (to reduce power consumption), this leads to the lost of the columns latches content. In this case, if columns latches were previously loaded they are reset: FLOAD bit in FSTA register should be reset after power down mode. If a power down mode is requested during flash programming (FBUSY=1), all power down sequence instructions should be ignored until the end of flash process.
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Reading the Flash Spaces User The following procedure is used to read the User space: * Read one byte in Accumulator by executing MOVC A,@A+DPTR
FCON is supposed to be reset when not needed. Note:
Depending of the MBO2:0 bits, the MOVC A,@A+DPTR can address a specific upper 32K bytes bank. It allows to read the 32K bytes upper On-chip flash memory from one bank to another one. When read from the bootloader area, the user memory shall be mapped before any read access by setting the FMR bit of the FSTA register. By default, when the bootloader is entered by hardware conditions, the ROM area is mapped for MOVC A,@A+DPTR operations. It is necessary to remap the user memory before each read access.
Extra Row (XAF)
The following procedure is used to read the Extra Row space and is summarized in Figure 17: * * * Map the Extra Row space by writing 01h in FCON register. Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h to 007Fh. Clear FCON to unmap the Extra Row.
Figure 17. XAF Reading Procedure
XRAW Reading
XRAW Mapping FCON = 01h
Data Read DPTR= @ (00h up to 7Fh ACC= 0 Exec: MOVC A, @A+DPTR
XRAW Unmapping FCON = 00h (FPS = 0)
Hardware Security Byte
The following procedure is used to read the Hardware Security space and is summarized in Figure 18:
* * * Map the Hardware Security space by writing 04h in FCON register. Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h. Clear FCON to unmap the Hardware Security Byte.
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Figure 18. HSB Reading Procedure
HSB Reading
HSB Mapping FCON = 04h
Data Read DPTR= 0000h ACC= 00h Exec: MOVC A, @A+DPTR
HSB Unmapping FCON = 00h (FPS = 0)
Fuse ConfigurationByte
The following procedure is used to read the Fuse Configuration byte and is summarized in Figure 18:
* * * Map the FCB by writing 05h in FCON register. Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h. Clear FCON to unmap the Hardware Security Byte.
HSB Reading Procedure
FCB Reading
FCB Mapping FCON = 05h
Data Read DPTR= 0000h ACC= 00h Exec: MOVC A, @A+DPTR
HSB Unmapping FCON = 00h (FPS = 0)
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Operation Cross Memory Access
Space addressable in read and write are: * * * * * * * * RAM ERAM (Expanded RAM access by movx) XRAM (eXternal RAM) FM0 (user flash) Hardware byte XROW FM0 Boot RM0 Flash Column latch
The table below provide the different kind of memory which can be accessed from different code location. Table 27. Cross Memory Access
XRAM Action Read boot RM0 Write Read FM0 Write External memory EA = 0 or BANK3 Read Write ok ok ok ok ok ok ok (idle) ok ok ok ok ok ok ok ok (RWW) ok ok (RWW) ok ok (RWW) ok ok (RWW) ok RAM ok ERAM ok boot RM0 ok FM0 ok HSB ok FCB ok XAF FM0 ok
Sharing Instructions
Table 28. Instructions shared
Action
Read
RAM
MOV
XRAM
MOVX A,@DPTR MOVX @DPTR,A
RM0
MOVC A, @A+DPTR -
CL FM0
MOVX @DPTR,A
FM0
MOVC A, @A+DPTR by CL FM0
HSB
MOVC A, @A+DPTR by CL FM0
XAF FM0
MOVC A, @A+DPTR by CL FM0
Write
MOV
Note:
by cl: using Column Latch
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Table 29. Write MOVX @DPTR,A
FPS of FCCON 0 1 0 winner EA X 1 XRAM ERAM winner winner CL FM0
Table 30. MOVC A, @A+DPTR executed from External code EA=0
FMOD2:0 X FBS (Fetch) X MBO (Target) X MOVC A,@A+DPTR Read External Code
Table 31. MOVC A, @A+DPTR executed from External code EA=1, PC>=0x8000, FBS=Bank3
FMOD2:0 MBO (Target) DPTR MOVC A,@A+DPTR Depends on FLB2:0 Can Returns Random value, for secured part. External code read
X
X X
< 0x8000 >= 0x8000
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Flash Protection from Parallel Programming
The three lock bits in Hardware Security Byte (see "In-System Programming" section) are programmed according to Table 32 provide different level of protection for the on-chip flash memory FM0. They are set by default to level 4 Table 32. Program Lock Bit FLB2-0
Program Lock Bits Security level 1 FLB0 U FLB1 U FLB2 U
Protection Description No program lock features enabled. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled. ISP allows only flash verification (no write operations are allowed) but IAP from internal code still allowed.
2
P
U
U
3 4
U U
P U
U P
Same as 2, also verify through parallel programming interface is disabled and ISP read operation not allowed. Same as 3, also external execution is disabled (external bank not accessible)
Program Lock bits U: unprogrammed P: programmed WARNING: Security level 2 and 3 should only be programmed after verification.
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Bootloader Architecture
Introduction
The bootloader manages a communication between a host platform running an ISP tool and a AT89C51RE2 target. The bootloader implemented in AT89C51RE2 is designed to reside in the dedicated ROM bank. This memory area can only be executed (fetched) when the processor enters the boot process. The implementation of the bootloader is based on standard set of libraries including INTEL hex based protocol, standard communication links and ATMEL ISP command set. Figure 19. Bootloader Functional Description
External Host with Specific Protocol Communication
ISP Communication Management
Bootloader
Memory Management
Memory
On the above diagram, the on-chip bootloader processes are: * ISP Communication Management The purpose of this process is to manage the communication and its protocol between the onchip bootloader and a external device. The on-chip ROM implement a serial protocol (see section Bootloader Protocol). This process translate serial communication frame (UART) into Flash memory access (read, write, erase...). * Memory Management This process manages low level access to Flash memory (performs read and write access).
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Bootloader Description
Entry points After reset only one bootloader entry point is possible. This entry point stands at address 0x0000 of the boot ROM memory. This entry point executes the boot process of the bootloader. The bootloader entry point can be selected through two processes: At reset, if the hardware conditions are applied, the bootloader entry point is accessed and executed. At reset, if the hardware conditions are not set and the BRV2-0 is programmed `011', the bootloader entry point is accessed and the bootprocess is started. Boot Process Description The boot process consists in three main operations: * * * The hardware boot process request detection The communication link detection (Uart or OCD) The start-up of the bootloader
RESET
Hardware Boot Process
No EA=1 PSEN=0
No
No
BRV='100'
No
BRV='101' BRV='110'
No
BRV='011'
Yes PC = FM0 Bank2 @0xFFFCh Yes Yes
Yes PC = FM0 Bank1 @0xFFFCh
Yes PC = FM0 Bank0 @0xFFFCh PC = FM0 Bank0 @0xFFFCh
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PC = RM0 @0x0000h
Communication link detector / initialiser
Start Bootloader Start Application
Hardware boot process request detection
The hardware boot process request is detected when the hardware conditions (under reset, EA=1 and PSEN=0) are received by the processor or when no hardware condition is applied and the BRV2:0 is configured `011'. Two interfaces are available for ISP: * * UART0 OCD UART
Communication link detection
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The communication link detection is done by a circular polling on all the interfaces. On AT89C51RE2, the ISP interfaces are all based on simple UART mechanisms (Rx, Tx). The Rx line default state is `1' when no communication is in progress. A transition from `1' to `0' on the Rx line indicates a start of frame. Once one of the interface detects a starts of frame (`0') on its Rx line, the interface is selected and configuration of the communication link starts. Figure 20. Communication link Detection
Detection Start
Interface 1
SF = 0
No
Yes
Interface 2
SF = 0
No
Yes
Interface 2 Initialisation
Interface 1 Initialisation
Start Bootloader
Notes:
1. SF: Start of Frame (`0' = detected; `1' = not detected) 2. In AT89C51RE2 implementation, Interface 1 refers to UART0 and Interface 2 refers to the OCD UART interface.
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ISP Protocol Description
Physical Layer The UART used to transmit information has the following configuration: * * * * * Character: 8-bit data Parity: none Stop: 1 bit Flow control: none Baud rate: autobaud is performed by the bootloader to compute the baud rate chosen by the host.
Frame Description
The Serial Protocol is based on the Intel Extended Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below. Table 33. Intel Hex Type Frame
Record Mark `:' 1 byte Record length 1 byte Load Offset 2 bytes Record Type 1 bytes Data or Info n byte Checksum 1 byte
* *
Record Mark: - - Record Mark is the start of frame. This field must contain':'. Record length specifies the number of Bytes of information or data which follows the Record Type field of the record. Load Offset specifies the 16-bit starting load offset of the data Bytes, therefore this field is used only for Data Program Record. Record Type specifies the command type. This field is used to interpret the remaining information within the frame. Data/Info is a variable length field. It consists of zero or more Bytes encoded as pairs of hexadecimal digits. The meaning of data depends on the Record Type. Checksum is the two's complement of the 8-bit Bytes that result from converting each pair of ASCII hexadecimal digits to one Byte of binary, thus including all field from the Record Length field to the last Byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, including all field from the Record Length field to the Checksum field, is zero. Record length:
*
Load Offset: - -
*
Record Type: -
*
Data/Info: -
*
Checksum: -
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Protocol
Overview An initialization step must be performed after each Reset. After microcontroller reset, the bootloader waits for an autobaud sequence (see Section "Autobaud Performances"). When the communication is initialized the protocol depends on the record type issued by the host. Communication Initialization The host initiates the communication by sending a 'U' character to help the bootloader to compute the baudrate (autobaud). Figure 21. Initialization Host Init Communication "U" Bootloader
Performs Autobaud Sends Back `U' Character
If (not received "U") Else Communication Opened
"U"
Autobaud Performances
The bootloader supports a wide range of baud rates. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency.
Command Data Stream Protocol All commands are sent using the same flow. To increase performance, the echo has been removed from the bootloader response. Figure 22. Command Flow Host Sends first character of the Frame ":" ":" Bootloader If (not received ":") Else Sends echo and start reception
Sends frame (made of 2 ASCII characters per Byte) Echo analysis
Gets frame, and sends back echo for each received Byte
Each command flow may end with:
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* * * * *
"X": If checksum error "L": If read security is set "P": If program security is set ".": If command ok byte + ".": read byte ok
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Reading/Blank checking memory Requests from Host
Command Read selected memory 04h Blank Check selected memory 05h 0000h Start Address End Address 01h Record Type Record Length Offset Data[0] Data[1] Data[2] Data[3] Data[4] 00h
To start the reading or blank checking operation,
Answers from Bootloader
The boot loader can answer to a read command with: * * * * * * * `Address = data `& `CR' &'LF' the number of data by line depends of the bootloader. `X' & `CR' & `LF' if the checksum is wrong `L' & `CR' & `LF' if the Security is set `.' & `CR' &'LF' when the blank check is ok `First Address wrong' `CR' & `LF' when the blank check is fail `X' & `CR' & `LF' if the checksum is wrong `L' & `CR' & `LF' if the Security is set
The bootloader answers to blank check command:
Changing memory/page
To change the memory selected and/or the page, the Host can send two commands. * * Select New Page to keep the same memory. Select Memory to change the Memory and page
Requests from Host
Command Select New Page Select Memory Record Type 02h 04h Record Length 02h 02h Offset start address 0000h Data[0] Page (4 bits) + 0h Memory space Data[1] 00h Page
Answers from Bootloader
The boot loader can answer to a read command with: * * `. `& `CR' &'LF' if the command is done `X' & `CR' & `LF' if the checksum is wrong
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Programming/Erasing memory Requests from Host
Command Program selected memory Erase selected memory Record Type 00h 04h Record Length nb of data 05h Offset start address 0000h Data[0] x 00h Data[1] x FFh Data[2] x 00h Data[3] x 00h Data[4] x 02h
Answers from Bootloader
The boot loader answers with: * * * `.' & `CR' &'LF' when the data are programmed `X' & `CR' & `LF' if the checksum is wrong `P' & `CR' & `LF' if the Security is set
Starting application
The application can only be started by a Watchdog reset. No answer is returned by the bootloader.
Requests from Host
Record Command Start application with watchdog Record Type 01h Length 00h Offset 0000h
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ISP Commands description
Select Memory Space The `Select Memory Space' command allows to route all read, write commands to a selected area. For each area (Family) a code is defined. This code corresponds to the memory area encoded value in the INTEL HEX frame. The area supported and there coding are listed in the table below. Table 34. Memory Families & coding
Memory/Information Family FLASH SECURITY CONFIGURATION BOOTLOADER SIGNATURE coding* 0 7 8 3 6 name MEM_FLASH MEM_PROTECT MEM_CONF MEM_BOOT MEM_SIGNATURE
The Bootloader information and the signature areas are read only. The value in the coding column is the value to report in the corresponding protocol field.
Note: * the coding number doesn't include any information on the authorized address range of the family. A summary of these addresses is available in appendix (See "Address Mapping" on page 67.)
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Select Page
The `Select Page' command allows to define a page number in the selected area. A page is defined as a 64K linear memory space (According to the INTEL HEX format). It doesn't corresponds to a physical bank from the processor. The following table summarizes the memory spaces for which the select page command can be applied. Table 35. Memory space & Select page
Memory/Information Family FLASH Comments/Restriction page 0 (0->64K) and 1(64k->128k) available
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Write commands The following table summarizes the memory spaces for which the write command can be applied. Table 36. Memory space & Select page
Memory/Information Family FLASH SECURITY CONFIGURATION Comments/Restriction need security level check only a higher level can be write
In case of write command to other area, nothing is done. The bootloader returns a Write protection (`P') if the SECURITY do not allow any write operation from the bootloader. FLASH The program/data Flash memory area can be programmed by the bootloader by data pages of up to 128bytes. If the Flash memory security level is at least `2' (FLB2:0 = `110'), no write operation can be performed through the bootloader. Table 37. Flash Write Authorization Summary
Security level (HSB) FLB2:0 Command Write 111 Allowed 110 Forbidden 101 Forbidden 011 Forbidden
CONFIGURATION SECURITY
The FCB configuration byte can always be written, whatever are the security levels. The Security byte can always be written with a value that enables a protection higher than the previous one. If attempting to write a lower security, no action is performed and the bootloader returns a protection error code (`P') Table 38. Security Write Authorization Summary
Security level (HSB) write from FLB2:0 111 110 101 011 111 Allowed Forbidden Forbidden Forbidden 110 Allowed Allowed Forbidden Forbidden
to FLB2:0
101 Allowed Allowed Allowed Forbidden 011 Allowed Allowed Allowed Allowed
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Erasing commands
The erasing command is supported by the following areas: Table 39. Memory space & Erase
Memory/Information Family FLASH Comments/Restriction need security level check
Nothing is done on the other areas. FLASH The erasing command on the Flash memory: * * erases the four physical flash memory banks (from address 0000h to 1FFFFh). the HSB (Hardware Security Byte) is set at NO_PROTECTION: - FLB2.0 = `111'
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Blank Checking commands The blank checking command is supported by the following areas Table 40. Memory space & Erase
Memory/Information Family FLASH Comments/Restriction need security level check
Nothing is done on the other areas. The first not erased address is returned if the blank check is failed. FLASH The blank checking command on the Flash memory can be done from address 0000h to 1FFFFh. The blank check operation is only possible if the HSB (Hardware Security Byte) has a security level lower than or equal to `2' (FLB2.0 = `110') Table 41. Flash Blank check Authorization Summary
Security level (HSB) FLB2:0 Command Blank Check 111 Allowed 110 Allowed 101 Forbidden 011 Forbidden
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Reading commands
The reading command is supported by the following areas: Table 42. Memory space & Select page
Memory/Information Family FLASH SECURITY CONFIGURATION BOOTLOADER SIGNATURE Comments/Restriction need security level check
FLASH
The reading command on the Flash memory can be done from address 000h to 1FFFFh. The read operation is only possible if the HSB (Hardware Security Byte) has a security level lower than or equal to `2' (FLB2.0 = `110') Table 43. Flash Read Authorization Summary
Security level (HSB) FLB2:0 Command Read 111 Allowed 110 Allowed 101 Forbidden 011 Forbidden
CONFIGURATION SECURITY BOOTLOADER
The CONFIGURATION family can always be read. The SECURITY family can always be read. All the field from the BOOTLOARED family can be read from the bootloader. Each bootloader information shall be read unitary. Accesses must be done byte per byte according to the address definition All the field from the SIGNATURE family can be read from the bootloader. Each signature information shall be read unitary. Accesses must be done byte per byte according to the address definition
SIGNATURE
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Start Application The start application command is used to quit the bootloader and start the application loaded. The start application is performed by a watchdog reset. The best way to start the application from a user defined entry point is to configure the FCB (Fuse Configuration Byte) before launching the watchdog. Then, depending on the configuration of the BRV2:0 field, the hardware boots from the selected memory area.
ISP Command summary UART Protocol frames Table 44. Summary of frames from Host
Command Program selected memory Start application with watchdog Select New Page Select Memory Read selected memory Blank Check selected memory Erase Selected memory 04h 05h 0000h 00h FFh 00h 00h Record Type 00h 01h 02h Record Length nb of data 00h 02h 02h Offset start address 0000h start address 0000h Data[0] x x Page (4 bits) + 0h Memory space Data[1] x x 00h Page Data[2] x x x x Data[3] x x x x Data[4] x x x x 00h Start Address End Address 01h 02h
Address Mapping Table 45. Memory Families, Addresses & Coding
Memory/Parameter FLASH HSB FCB Bootloader revision Boot id1 Boot id2 Manuf. code Family code 6 Product name Product rev 60h 61h 3 coding 0 7 8 Address 0 up to 0x1FFFF 0 0 00h 01h 02h 30h 31h 0 SIGNATURE 0 BOOTLOADER Page number 0 up to 1 0 0 Memory/Information Family FLASH SECURITY CONFIGURATION
Attempting an access with any other `coding', `page number' or `Address' results in no action and no answer from the bootloader.
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Timers/Counters
The AT89C51RE2 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections. A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 46) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divideddown peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is FPER/6, i.e. FOSC/12 in standard mode or FOSC/6 in X2 mode. For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is FPER/12, i.e. FOSC/24 in standard mode or FOSC/12 in X2 mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle.
Timer/Counter Operations
Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 23 to Figure 26 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (see Figure 47) and bits 0, 1, 4 and 5 of TCON register (see Figure 46). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt request. It is important to stop Timer/Counter before changing mode.
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Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 23). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register.
Figure 23. Timer/Counter x (x = 0 or 1) in Mode 0
See the "Clock" section
FTx CLOCK /6 0 1
THx (8 bits)
TLx (5 bits)
Overflow
TFx
TCON reg
Tx C/Tx#
TMOD reg
Timer x Interrupt Request
INTx# GATEx
TMOD reg
TRx
TCON reg
Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 24). The selected input increments TL0 register.
Figure 24. Timer/Counter x (x = 0 or 1) in Mode 1
See the "Clock" section
FTx CLOCK /6 0 1
THx (8 bits)
TLx (8 bits)
Overflow
TFx
TCON reg
Tx C/Tx#
TMOD reg
Timer x Interrupt Request
INTx# GATEx
TMOD reg
TRx
TCON reg
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Mode 2 (8-bit Timer with Auto-Reload)
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 25). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register.
Figure 25. Timer/Counter x (x = 0 or 1) in Mode 2
See the "Clock" section
FTx CLOCK /6 0 1
TLx (8 bits)
Overflow
TFx
TCON reg
Tx C/Tx#
TMOD reg
Timer x Interrupt Request
INTx# GATEx
TMOD reg
TRx
TCON reg
THx (8 bits)
Mode 3 (Two 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 26). This mode is provided for applications requiring an additional 8-bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting FPER /6) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3.
Figure 26. Timer/Counter 0 in Mode 3: Two 8-bit Counters
FTx CLOCK /6 0 1
TL0 (8 bits)
Overflow
TF0
TCON.5
T0 C/T0#
TMOD.2
Timer 0 Interrupt Request
INT0# GATE0
TMOD.3
TR0
TCON.4
FTx CLOCK
/6
TH0 (8 bits) TR1
TCON.6
Overflow
TF1
TCON.7
Timer 1 Interrupt Request
See the "Clock" section
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Timer 1
Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The following comments help to understand the differences: * Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 23 to Figure 25 show the logical configuration for modes 0, 1, and 2. Timer 1's mode 3 is a hold-count mode. Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 47) and bits 2, 3, 6 and 7 of TCON register (see Figure 46). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1). Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation. Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request. When Timer 0 is in mode 3, it uses Timer 1's overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. It is important to stop Timer/Counter before changing mode.
*
* * * *
* Mode 0 (13-bit Timer)
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 23). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register. Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 24). The selected input increments TL1 register. Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (see Figure 25). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3. Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.
Mode 1 (16-bit Timer)
Mode 2 (8-bit Timer with Auto-Reload)
Mode 3 (Halt)
Interrupt
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Figure 27. Timer Interrupt System
TF0
TCON.5
Timer 0 Interrupt Request ET0
IEN0.1
TF1
TCON.7
Timer 1 Interrupt Request ET1
IEN0.3
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Registers
Table 46. TCON Register TCON (S:88h) Timer/Counter Control Register
7 TF1 6 TR1 Bit Mnemonic 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
Bit Number
Description Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin. Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin. Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Reset Value = 0000 0000b
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Table 47. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register
7 GATE1 6 C/T1# Bit Mnemonic 5 M11 4 M01 3 GATE0 2 C/T0# 1 M10 0 M00
Bit Number
Description Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. Timer 1 Mode Select Bits M01 M11 0 0 0 1 1 0 1 1
7
GATE1
6
C/T1#
5
M11
4
M01
Operating mode Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). Mode 1: 16-bit Timer/Counter. Mode 2: 8-bit auto-reload Timer/Counter (TL1)(1) Mode 3: Timer 1 halted. Retains count
3
GATE0
Timer 0 Gating Control Bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. Timer 0 Counter/Timer Select Bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. Timer 0 Mode Select Bit M00 Operating mode M10 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0)(2) 1 1 Mode 3: TL0 is an 8-bit Timer/Counter TH0 is an 8-bit Timer using Timer 1's TR0 and TF0 bits.
2
C/T0#
1
M10
0
M00
Notes: 1. Reloaded from TH1 at overflow. 2. Reloaded from TH0 at overflow. Reset Value = 0000 0000b
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Table 48. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register
7 - 6 - Bit Mnemonic 5 - 4 - 3 - 2 - 1 - 0 -
Bit Number 7:0
Description High Byte of Timer 0.
Reset Value = 0000 0000b Table 49. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register
7 - 6 - Bit Mnemonic 5 - 4 - 3 - 2 - 1 - 0 -
Bit Number 7:0
Description Low Byte of Timer 0.
Reset Value = 0000 0000b Table 50. TH1 Register TH1 (S:8Dh) Timer 1 High Byte Register
7 - 6 - Bit Mnemonic 5 - 4 - 3 - 2 - 1 - 0 -
Bit Number 7:0
Description High Byte of Timer 1.
Reset Value = 0000 0000b
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Table 51. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register
7 - 6 - Bit Mnemonic 5 - 4 - 3 - 2 - 1 - 0 -
Bit Number 7:0
Description Low Byte of Timer 1.
Reset Value = 0000 0000b
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Timer 2
The Timer 2 in the AT89C51RE2 is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is controlled by T2CON (Table 52) and T2MOD (Table 53) registers. Timer 2 operation is similar to Timer 0 and Timer 1.C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to increment by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON). Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. Timer 2 includes the following enhancements: * * Auto-reload mode with up or down counter Programmable clock-output
Auto-Reload Mode The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic
reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter as shown in Figure 28. In this mode the T2EX pin controls the direction of count. When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.
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Figure 28. Auto-Reload Mode Up/Down Counter (DCEN = 1) FCLK PERIPH :6
T2 C/T2 T2CON TR2 T2CON 0 1
T2EX: (DOWN COUNTING RELOAD VALUE) if DCEN=1, 1=UP FFh FFh if DCEN=1, 0=DOWN (8-bit) (8-bit) if DCEN = 0, up counting
TOGGLE T2CON EXF2
TL2
(8-bit)
TH2
(8-bit)
TF2 T2CON
TIMER 2 INTERRUPT
RCAP2L (8-bit)
RCAP2H (8-bit)
(UP COUNTING RELOAD VALUE)
Programmable Clock-Output
In the clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 29). The input clock increments TL2 at frequency FCLK PERIPH/2.The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2.In this mode, Timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers: F CLKPERIPH Clock - O utFrequency = -------------------------------------------------------------------------------------------4 x ( 65536 - RCAP2H RCAP2L ) For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz (FCLK PERIPH/216) to 4 MHz (FCLK PERIPH/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: * * * * * Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. Enter a 16-bit initial value in timer registers TH2/TL2.It can be the same as the reload value or a different one depending on the application. To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.
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Figure 29. Clock-Out Mode C/T2 = 0
FCLK PERIPH :6
TR2
T2CON
TL2 (8-bit)
TH2 (8-bit)
OVERFLOW
RCAP2L RCAP2H (8-bit) (8-bit)
Toggle T2
Q
D T2OE T2MOD
T2EX EXEN2 T2CON
EXF2 T2CON
TIMER 2 INTERRUPT
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Registers
Table 52. T2CON Register T2CON - Timer 2 Control Register (C8h)
7 TF2 Bit Number 6 EXF2 Bit Mnemonic Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn't cause an interrupt in Up/down counter mode (DCEN = 1). Receive Clock bit Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock bit Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Cleared to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port. Timer 2 Run control bit Cleared to turn off Timer 2. Set to turn on Timer 2. Timer/Counter 2 select bit Cleared for timer operation (input from internal clock system: FCLK PERIPH). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2#
7
TF2
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Reset Value = 0000 0000b Bit addressable
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Table 53. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h)
7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. 5 4 3 2 1 T2OE 0 DCEN
6
-
5
-
4
-
3
-
2
-
1
T2OE
0
DCEN
Reset Value = XXXX XX00b Not bit addressable
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Programmable Counter Array PCA
The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any one of the following signals: * * * * * * * * Peripheral clock frequency (FCLK PERIPH) / 2 Timer 0 overflow External input on ECI (P1.2) Rising and/or falling edge capture Software timer High-speed output Pulse width modulator Peripheral clock frequency (FCLK PERIPH)
/6
Each compare/capture modules can be programmed in any one of the following modes:
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 93). When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O.
PCA component 16-bit Counter 16-bit Module 0 16-bit Module 1 16-bit Module 2 16-bit Module 3 External I/O Pin P1.2 / ECI P1.3 / CEX0 P1.4 / CEX1 P1.5 / CEX2 P1.6 / CEX3
The PCA timer is a common time base for all five modules (See Figure 30). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 54) and can be programmed to run at: * * * * 1/6 the peripheral clock frequency (FCLK PERIPH) 1/2 the peripheral clock frequency (FCLK PERIPH) The Timer 0 overflow The input on the ECI pin (P1.2)
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Figure 30. PCA Timer/Counter
To PCA modules Fclk periph /6 Fclk periph / 2 T0 OVF P1.2 CH CL 16 bit up/down counter overflow It
CIDL Idle
WDTE
CPS1
CPS0
ECF
CMOD 0xD9
CF
CR
CCF4 CCF3
CCF2
CCF1
CCF0
CCON 0xD8
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Table 54. CMOD Register CMOD - PCA Counter Mode Register (D9h)
7 CIDL Bit Number 6 WDTE Bit Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Watchdog Timer Enable 6 WDTE Cleared to disable Watchdog Timer function on PCA Module 4. Set to enable Watchdog Timer function on PCA Module 4. 5 Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Count Pulse Select CPS1 CPS0 Selected PCA input 0 0 Internal clock fCLK PERIPH/6 1 CPS0 0 1 1 1 0 1 Internal clock fCLK PERIPH/2 Timer 0 Overflow External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4) 5 4 3 2 CPS1 1 CPS0 0 ECF
4
-
3 2
CPS1
0
ECF
PCA Enable Counter Overflow Interrupt Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt.
Reset Value = 00XX X000b Not bit addressable The CMOD register includes three additional bits associated with the PCA (See Figure 30 and Table 54). * * * The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the watchdog function on module 4. The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (Refer to Table 55). * * Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software.
*
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Table 55. CCON Register CCON - PCA Counter Control Register (D8h)
7 CF Bit Number 6 CR Bit Mnemonic Description PCA Counter Overflow flag 7 CF Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit 6 CR Must be cleared by software to turn the PCA counter off. Set by software to turn the PCA counter on. 5 Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Module 4 interrupt flag 4 CCF4 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 3 interrupt flag 3 CCF3 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 2 interrupt flag 2 CCF2 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 1 interrupt flag 1 CCF1 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 0 interrupt flag 0 CCF0 Must be cleared by software. Set by hardware when a match or capture occurs. 5 4 CCF4 3 CCF3 2 CCF2 1 CCF1 0 CCF0
Reset Value = 00X0 0000b Not bit addressable The watchdog timer function is implemented in module 4 (See Figure 33). The PCA interrupt system is shown in Figure 31.
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Figure 31. PCA Interrupt System
CF PCA Timer/Counter CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8
Module 0
Module 1
To Interrupt priority decoder
Module 2
Module 3
Module 4 CMOD.0 ECF ECCFn CCAPMn.0 IE.6 EC IE.7 EA
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: * * * * * * 16-bit Capture, positive-edge triggered 16-bit Capture, negative-edge triggered 16-bit Capture, both positive and negative-edge triggered 16-bit Software Timer 16-bit High Speed Output 8-bit Pulse Width Modulator
In addition, module 4 can be used as a Watchdog Timer. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 56). The registers contain the bits that control the mode that each module will operate in. * The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
* *
*
*
*
Table 56 shows the CCAPMn settings for the various PCA functions.
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Table 56. CCAPMn Registers (n = 0-4) CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
7 Bit Number 7 6 ECOMn Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Enable Comparator 6 ECOMn Cleared to disable the comparator function. Set to enable the comparator function. Capture Positive 5 CAPPn Cleared to disable positive edge capture. Set to enable positive edge capture. Capture Negative 4 CAPNn Cleared to disable negative edge capture. Set to enable negative edge capture. Match 3 MATn When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle 2 TOGn When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode 1 PWMn Cleared to disable the CEXn pin to be used as a pulse width modulated output. Set to enable the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt 0 CCF0 Cleared to disable compare/capture flag CCFn in the CCON register to generate an interrupt. Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt. 5 CAPPn 4 CAPNn 3 MATn 2 TOGn 1 PWMn 0 ECCFn
Reset Value = X000 0000b Not bit addressable
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Table 57. PCA Module Modes (CCAPMn Registers)
ECOMn 0 X CAPPn 0 1 CAPNn 0 0 MATn 0 0 TOGn 0 0 PWMm 0 0 ECCFn 0 X Module Function No Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger on CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer / Compare mode. 16-bit High Speed Output 8-bit PWM Watchdog Timer (module 4 only)
X X 1 1 1 1
0 1 0 0 0 0
1 1 0 0 0 0
0 0 1 1 0 1
0 0 0 1 0 X
0 0 0 0 1 0
X X X X 0 X
There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 58 & Table 59). Table 58. CCAPnH Registers (n = 0-4) CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh) CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh) CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh) CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
7 Bit Number 7-0 6 Bit Mnemonic Description PCA Module n Compare/Capture Control CCAPnH Value 5 4 3 2 1 0 -
Reset Value = 0000 0000b Not bit addressable
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Table 59. CCAPnL Registers (n = 0-4) CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
7 Bit Number 7-0 6 Bit Mnemonic Description PCA Module n Compare/Capture Control CCAPnL Value 5 4 3 2 1 0 -
Reset Value = 0000 0000b Not bit addressable Table 60. CH Register CH - PCA Counter Register High (0F9h)
7 Bit Number 7-0 6 Bit Mnemonic Description PCA counter CH Value 5 4 3 2 1 0 -
Reset Value = 0000 0000b Not bit addressable Table 61. CL Register CL - PCA Counter Register Low (0E9h)
7 Bit Number 7-0 6 Bit Mnemonic Description PCA Counter CL Value 5 4 3 2 1 0 -
Reset Value = 0000 0000b Not bit addressable
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PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits
CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 32). Figure 32. PCA Capture Mode
CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA IT
PCA Counter/Timer Cex.n Capture CH CL
CCAPnH
CCAPnL
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE
16-bit Software Timer/ Compare Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 33).
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Figure 33. PCA Compare Mode and PCA Watchdog Timer
CCON CF Write to CCAPnL Write to CCAPnH 1 0 Enable 16 bit comparator RESET * Reset PCA IT CCAPnH CCAPnL Match CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8
CH
CL
PCA counter/timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4 0xDA to 0xDE
CIDL
WDTE
CPS1 CPS0
ECF
CMOD 0xD9
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn't occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
High Speed Output In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this Mode
mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 34). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
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Figure 34. PCA High Speed Output Mode
CCON CF CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8
Write to CCA PnL Reset
PCA IT Write to CCAPnH 0 CCAPnH Enable 16 bit comparator CCAPnL Match
1
CH
CL
CEXn
PCA counter/timer CCAPMn, n = 0 to 4 0xDA to 0xDE
ECO Mn CAPPn CAPNn MATn TOGn PWMn ECCFn
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn't occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
Pulse Width Modulator Mode
All of the PCA modules can be used as PWM outputs. Figure 35 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
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Figure 35. PCA PWM Mode
CCAPnH Overflow
CCAPnL "0" Enable 8 bit comparator "1" CL PCA counter/timer CEXn
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n= 0 to 4 0xDA to 0xDE
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 33 shows a diagram of how the watchdog works. The user preloads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the PCA timer, 2. periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won't generate a reset out on the reset pin.
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Serial I/O Port
The serial I/O ports in the AT89C51RE2 are compatible with the serial I/O port in the 80C52. They provide both synchronous and asynchronous communication modes. They operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Both serial I/O port include the following enhancements: * * Framing error detection Automatic address recognition
As these improvements apply to both UART, most of the time in the following lines, there won't be any reference to UART_0 or UART_1, but only to UART, generally speaking.
Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 36) for UART 0 or set SMOD0_1 in BDRCON_1 register for UART 1 (See Figure 37). Figure 36. UART 0 Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON_0 (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART 0 mode control (SMOD0 = 0) SM0D1 SMOD0 POF GF1 GF0 PD IDL PCON (87h)
To UART 0 framing error control
Figure 37. UART 1 Framing Error Block Diagram
SM0_1/FE_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
SCON_1 (C0h)
Set FE_1 bit if stop bit is 0 (framing error) (SMOD0_1 = 1) SM0 to UART 1 mode control (SMOD0_1 = 0) SM0D1_1SMOD0_1 BRR_1 TBCK_1 RBCK_1 SPD_1 SRC_1 BDRCON_1 (87h)
To UART 1 framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 68.) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 38 and Figure 39).
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Figure 38. UART Timings in Mode 1
RXD Start bit RI SMOD0=X FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 Stop bit
Data byte
Figure 39. UART Timings in Modes 2 and 3
RXD Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 D8 Ninth Stop bit bit
Data byte
Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, the user may enable the automatic address recognition feature in mode 1.In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don't-care bits (defined by zeros) to form the device's given address. The don't-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:
SADDR0101 0110b SADEN1111 1100b Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
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Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't-care bit; for slaves B and C, bit 0 is a 1.To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't-care bits, e.g.:
SADDR0101 0110b SADEN1111 1100b Broadcast =SADDR OR SADEN1111 111Xb
The use of don't-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B, Slave C:SADDR=1111 0011b SADEN1111 1101b Broadcast1111 1111b
For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and broadcast addresses are XXXX XXXXb (all don't-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition.
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Registers
Table 62. SADEN_0 Register SADEN - Slave Address Mask Register UART 0(B9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Not bit addressable Table 63. SADDR_0 Register SADDR - Slave Address Register UART 0(A9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Not bit addressable Table 64. SADEN_1 Register SADEN_1 - Slave Address Mask Register UART 1(BAh)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Not bit addressable Table 65. SADDR_1 Register SADDR_1 - Slave Address Register UART 1(AAh)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Not bit addressable
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Baud Rate The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON_0 registers. Selection for UART 0 for Mode 1 Figure 40. Baud Rate Selection for UART 0 and 3
TIMER1 TIMER2 0 1 RCLK INT_BRG RBCK TIMER_BRG_RX 0 1 / 16 Rx Clock_0
TIMER1 TIMER2
0 1 TCLK
TIMER_BRG_TX 0 1 / 16 Tx Clock_0
INT_BRG
TBCK
Table 66. Baud Rate Selection Table UART 0
TCLK (T2CON) RCLK (T2CON) TBCK (BDRCON) RBCK (BDRCON) Clock Source UART Tx Clock Source UART Rx
0 1 0 1 X X 0 1 X
0 0 1 1 0 1 X X X
0 0 0 0 1 1 0 0 1
0 0 0 0 0 0 1 1 1
Timer 1 Timer 2 Timer 1 Timer 2 INT_BRG INT_BRG Timer 1 Timer 2 INT_BRG
Timer 1 Timer 1 Timer 2 Timer 2 Timer 1 Timer 2 INT_BRG INT_BRG INT_BRG
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Baud Rate The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON_1 registers. Selection for UART 1 for Mode 1 Figure 41. Baud Rate Selection for UART 1 and 3
TIMER1 TIMER2 0 1 RCLK INT_BRG1 RBCK_1 TIMER_BRG_RX 0 1 / 16 Rx Clock_1
TIMER1 TIMER2
0 1 TCLK
TIMER_BRG_TX 0 1 / 16 Tx Clock_1
INT_BRG1
TBCK_1
Table 67. Baud Rate Selection Table UART 1
TCLK (T2CON) RCLK (T2CON) TBCK_1 (BDRCON_1) RBCK_1 (BDRCON_1) Clock Source UART Tx_1 Clock Source UART Rx_1
0 1 0 1 X X 0 1 X
0 0 1 1 0 1 X X X
0 0 0 0 1 1 0 0 1
0 0 0 0 0 0 1 1 1
Timer 1 Timer 2 Timer 1 Timer 2 INT_BRG_1 INT_BRG_1 Timer 1 Timer 2 INT_BRG_1
Timer 1 Timer 1 Timer 2 Timer 2 Timer 1 Timer 2 INT_BRG_1 INT_BRG_1 INT_BRG_1
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Internal Baud Rate Generator (BRG)
The AT89C51RE2 implements two internal baudrate generators. Each one is dedicated to the corresponding UART. The configuration and operating mode for both BRG are similar. When an internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL (BRL or BRL_1 registers) reload value, the value of SPD (or SPD_1) bit (Speed Mode) in BDRCON (BDRCON_1) register and the value of the SMOD1 bit in PCON register.
Figure 42. Internal Baud Rate generator 0
FPER /6 0 1 SPD_0 BRR_0 BRL_0 SMOD1 auto reload counter overflow BRG /2 0 1 INT_BRG
Figure 43. Internal Baud Rate generator 1
FPER /6 0 1 SPD_1 BRR_1 BRL_1 SMOD1_1 auto reload counter overflow BRG /2 0 1 INT_BRG1
*
The baud rate for UART is token by formula:
2SMOD1 FPER 6(1-SPD) 32 (256 -BRL) 2SMOD1 FPER 32 Baud_Rate
Baud_Rate =
BRL = 256 -
6
(1-SPD)
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Table 68. SCON_0 register SCON_0 - Serial Control Register for UART 0(98h)
7 6 5 4 3 2 1 0
FE/SM0_0
Bit Number
SM1_0
Bit Mnemonic
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
Description Framing Error bit (SMOD0=1)
FE_0 7 SM0_0
Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit.
Serial port Mode bit 0 Refer to SM1_0 for serial port mode selection.
SMOD0_0 must be cleared to enable access to the SM0_0 bit.
Serial port Mode bit 1 SM0 SM1 Mode Description
Baud Rate FCPU PERIPH/6 Variable FCPU PERIPH /32 or /16 Variable
6
SM1_0
0 0 1 1
0 1 0 1
0 1 2 3
Shift Register 8-bit UART 9-bit UART 9-bit UART
Serial port Mode 2 bit / Multiprocessor Communication Enable bit 5 SM2_0 Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit Clear to disable serial reception. Set to enable serial reception.
4
REN_0
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 3 TB8_0 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.
2
RB8_0
In mode 1, if SM2_0 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 38. and Figure 39. in the other modes.
1
TI_0
0
RI_0
Reset Value = 0000 0000b Bit addressable
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Table 69. SCON_1 Register SCON_1 - Serial Control Register for UART 1(C0h)
7 6 5 4 3 2 1 0
FE/SM0_1
Bit Number
SM1_1
Bit Mnemonic
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
Description Framing Error bit (SMOD0=1)
FE_1 7 SM0_1
Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0_1 must be set to enable access to the FE_1 bit.
Serial port Mode bit 0 Refer to SM1_1 for serial port mode selection.
SMOD0_1 must be cleared to enable access to the SM0_1 bit.
Serial port Mode bit 1 SM0 SM1 Mode Description
Baud Rate FCPU PERIPH/6 Variable FCPU PERIPH /32 or /16 Variable
6
SM1_1
0 0 1 1
0 1 0 1
0 1 2 3
Shift Register 8-bit UART 9-bit UART 9-bit UART
Serial port Mode 2 bit / Multiprocessor Communication Enable bit 5 SM2_1 Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit Clear to disable serial reception. Set to enable serial reception.
4
REN_1
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 3 TB8_1 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.
2
RB8_1
In mode 1, if SM2_1 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 38. and Figure 39. in the other modes.
1
TI_1
0
RI_1
Reset Value = 0000 0000b Bit addressable
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Table 70. Example of Computed Value When X2=1, SMOD1=1, SPD=1
Baud Rates FOSC = 16. 384 MHz BRL Error (%) BRL FOSC = 24MHz Error (%)
115200 57600 38400 28800 19200 9600 4800
247 238 229 220 203 149 43
1.23 1.23 1.23 1.23 0.63 0.31 1.23
243 230 217 204 178 100 -
0.16 0.16 0.16 0.16 0.16 0.16 -
Table 71. Example of Computed Value When X2=0, SMOD1=0, SPD=0
Baud Rates FOSC = 16. 384 MHz BRL Error (%) BRL FOSC = 24MHz Error (%)
4800 2400 1200 600
247 238 220 185
1.23 1.23 1.23 0.16
243 230 202 152
0.16 0.16 3.55 0.16
The baud rate generator can be used for mode 1 or 3 (refer to Figure 40.), but also for mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 78.)
UART Registers
Table 72. SBUF_0 register SBUF_0 - Serial Buffer Register for UART 0(99h)
7 6 5 4 3 2 1 0
Reset Value = XXXX XXXXb Table 73. BRL_0 register BRL_0 - Baud Rate Reload Register for the internal baud rate generator 0 (9Ah)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b
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Table 74. SBUF_1 Register SBUF - Serial Buffer Register for UART 1(C1h)
7 6 5 4 3 2 1 0
Reset Value = XXXX XXXXb Table 75. BRL_1 Register BRL - Baud Rate Reload Register for the internal baud rate generator 1 (BBh)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b
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Table 76. T2CON Register T2CON - Timer 2 Control Register (C8h)
7 TF2 Bit Number 6 EXF2 Bit Mnemonic Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn't cause an interrupt in Up/down counter mode (DCEN = 1) Receive Clock bit for UART Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock bit for UART Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Cleared to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run control bit Cleared to turn off timer 2. Set to turn on timer 2. Timer/Counter 2 select bit Cleared for timer operation (input from internal clock system: FCLK PERIPH). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2#
7
TF2
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Reset Value = 0000 0000b Bit addressable
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Table 77. PCON Register PCON - Power Control Register (87h)
7 SMOD1_0 Bit Number 6 SMOD0_0 Bit Mnemonic Description Serial port Mode bit 1 for UART Set to select double baud rate in mode 1, 2 or 3. 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL
7
SMOD1_0
Serial port Mode bit 0 for UART 6 SMOD0_0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register.
Reserved The value read from this bit is indeterminate. Do not set this bit. Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode.
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn't affect the value of this bit.
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Table 78. BDRCON_0 Register BDRCON_0 - Baud Rate Control Register (9Bh)
7 Bit Number 6 Bit Mnemonic 5 4 BRR_0 3 TBCK_0 2 RBCK_0 1 SPD_0 0 SRC_0
Description Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit. Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. Transmission Baud rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Reception Baud Rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Baud Rate Speed Control bit for UART Cleared to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART
7
-
6
-
5
-
4
BRR_0
3
TBCK_0
2
RBCK_0
1
SPD_0
0
SRC_0
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = XXX0 0000b Not bit addressable
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Table 79. BDRCON_1 Register BDRCON - Baud Rate Control Register (BCh)
7 SMOD1_1 Bit Number 6 SMOD0_1 Bit Mnemonic 5 4 BRR_1 3 TBCK_1 2 RBCK_1 1 SPD_1 0 SRC_1
Description Serial port Mode bit 1 for UART 1 Set to select double baud rate in mode 1, 2 or 3.
7
SMOD1_1
Serial port Mode bit 0 for UART 1 6 SMOD0_1 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register.
Reserved The value read from this bit is indeterminate. Do not set this bit. Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. Transmission Baud rate Generator Selection bit for UART 1 Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Reception Baud Rate Generator Selection bit for UART 1 Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Baud Rate Speed Control bit for UART 1 Cleared to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART 1
5
-
4
BRR_1
3
TBCK_1
2
RBCK_1
1
SPD_1
0
SRC_1
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = 0000 0000b Not bit addressable
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Interrupt System
The AT89C51RE2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), two serial ports interrupts, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 44.
Figure 44. Interrupt Control System
IPH, IPL 3 INT0 IE0 0 3 TF0 0 3 INT1 IE1 0 3 TF1 0 3
PCA IT
High priority interrupt
Interrupt polling sequence, decreasing from high to low priority
0 RI TI 3 0 3 0 3
KBD IT
TF2 EXF2
0 3 TWI IT 0 3 SPI IT 0 RI_1 TI_1 3 0 Low priority interrupt Individual Enable Global Disable
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 84 and Table 82). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 85) and in the Interrupt Priority High register (Table 83 and Table 84) shows the bit values and priority levels associated with each combination.
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Registers
Table 80. Priority Level Bit Values
iph. x ipl. x interrupt level priority
0 0 1 1
0 1 0 1
0 (lowest) 1 2 3 (highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence.
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Table 81. IEN0 Register IEN0 - Interrupt Enable Register (A8h)
7 EA Bit Number 6 EC Bit Mnemonic Description Enable All interrupt bit Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
7
EA
6
EC
Cleared to disable. Set to enable.
Timer 2 overflow interrupt Enable bit Cleared to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. Serial port 0 Enable bit Cleared to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 overflow interrupt Enable bit Cleared to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External interrupt 1 Enable bit Cleared to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit Cleared to disable external interrupt 0. Set to enable external interrupt 0.
5
ET2
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Reset Value = 0000 0000b Bit addressable
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Table 82. IPL0 Register IPL0 - Interrupt Priority Register (B8h)
7 Bit Number 6 PPCL Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. Serial port 0 Priority bit Refer to PSH for priority level. Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. External interrupt 1 Priority bit Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. External interrupt 0 Priority bit Refer to PX0H for priority level. 5 PT2L 4 PSL 3 PT1L 2 PX1L 1 PT0L 0 PX0L
7
-
6
PPCL
5
PT2L
4
PSL
3
PT1L
2
PX1L
1
PT0L
0
PX0L
Reset Value = X000 0000b Bit addressable
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Table 83. IPH0 Register IPH0 - Interrupt Priority High Register (B7h)
7 6 5 4 3 2 1 0
Bit Number
PPCH
Bit Mnemonic
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority high bit. PPCH PPCL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 2 overflow interrupt Priority High bit PT2H PT2L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Serial port Priority High bit PSH PSL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 1 overflow interrupt Priority High bit PT1H PT1L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 1 Priority High bit PX1H PX1L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 overflow interrupt Priority High bit PT0H PT0L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 0 Priority High bit PX0H PX0L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest
7
-
6
PPCH
5
PT2H
4
PSH
3
PT1H
2
PX1H
1
PT0H
0
PX0H
Reset Value = X000 0000b Not bit addressable
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Table 84. IEN1 Register IEN1 - Interrupt Enable Register (B1h)
7 6 5 4 3 2 1 0
Bit Number
Bit Mnemonic
-
-
ES_1
ESPI
ETWI
EKBD
Description Reserved Reserved Reserved Reserved Serial port 1 Enable bit Cleared to disable serial port interrupt. Set to enable serial port interrupt. SPI interrupt Enable bit Cleared to disable SPI interrupt.
7 6 5 4
-
3
ES_1
2
ESPI
Set to enable SPI interrupt.
TWI interrupt Enable bit
1
ETWI
Cleared to disable TWI interrupt. Set to enable TWI interrupt.
Keyboard interrupt Enable bit Cleared to disable keyboard interrupt. Set to enable keyboard interrupt.
0
EKBD
Reset Value = XXXX 00x0b Bit addressable
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Table 85. IPL1 Register IPL1 - Interrupt Priority Register (B2h)
7 Bit Number 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Serial port 1 Priority bit Refer to PSH_1 for priority level. SPI interrupt Priority bit Refer to SPIH for priority level. TWI interrupt Priority bit 5 4 3 PSL_1 2 SPIL 1 TWIL 0 KBDL
7
-
6
-
5
-
4
-
3
PSL_1
2
SPIL
1
TWIL
Refer to TWIH for priority level.
Keyboard interrupt Priority bit Refer to KBDH for priority level.
0
KBDL
Reset Value = XXXX 00X0b Bit addressable
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Table 86. IPH1 Register IPH1 - Interrupt Priority High Register (B3h)
7 Bit Number 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Serial port 1 Priority High bit PSH_1 PSL_1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest SPI interrupt Priority High bit SPIH SPIL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest TWI interrupt Priority High bit TWIH TWIL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Keyboard interrupt Priority High bit KB DH KBDL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest 5 4 3 PSH_1 2 SPIH 1 TWIH 0 KBDH
7
-
6
-
5
-
4
-
3
PSH_1
2
SPIH
1
TWIH
0
KBDH
Reset Value = XXXX 00X0b Not bit addressable
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Interrupt Sources and Vector Addresses
Table 87. Interrupt Sources and Vector Addresses
Number Polling Priority Interrupt Source Interrupt Request Vector Address
0 1 2 3 4 5 6 7 8 9 10 11
0 1 2 3 4 6 7 5 8 9 10 11
Reset INT0 Timer 0 INT1 Timer 1 UART0 Timer 2 PCA Keyboard TWI SPI UART1 IE0 TF0 IE1 IF1 RI+TI TF2+EXF2 CF + CCFn (n = 0-4) KBDIT TWIIT SPIIT RI_1+TI_1
0000h 0003h 000Bh 0013h 001Bh 0023h 002Bh 0033h 003Bh 0043h 004Bh 0053h
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Power Management
Introduction
Two power reduction modes are implemented in the AT89C51RE2. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section "Enhanced Features", page 13.
Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 88. To enter Idle mode, set the IDL bit in PCON register (see Table 89). The AT89C51RE2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed.
Note: If IDL bit and PD bit are set simultaneously, the AT89C51RE2 enters Power-Down mode. Then it does not go in Idle mode when exiting Power-Down mode.
Entering Idle Mode
Exiting Idle Mode
There are two ways to exit Idle mode: 1. Generate an enabled interrupt. - Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT89C51RE2 and vectors the CPU to address C:0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM.
2. Generate a reset. -
Note:
Power-Down Mode The Power-Down mode places the AT89C51RE2 in a very low power state. Power-Down mode
stops the oscillator, freezes all clock at known states. The CPU status prior to entering PowerDown mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-Down mode. In addition, the SFR and RAM contents are preserved. The status of the Port pins during Power-Down mode is detailed in Table 88.
Note: VCC may be reduced to as low as VRET during Power-Down mode to further reduce power dissipation. Take care, however, that VDD is not reduced until Power-Down mode is invoked.
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Entering Power-Down Mode To enter Power-Down mode, set PD bit in PCON register. The AT89C51RE2 enters the PowerDown mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed.
Exiting Power-Down Mode
Note:
If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is restored to the normal operating level.
There are two ways to exit the Power-Down mode: 1. Generate an enabled external interrupt. - The AT89C51RE2 provides capability to exit from Power-Down using INT0#, INT1#. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTx# input, execution resumes when the input is released (see Figure 45). Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-Down mode.
The external interrupt used to exit Power-Down mode must be configured as level sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.
Note:
Note:
Figure 45. Power-Down Exit Waveform Using INT1:0#
INT1:0#
OSC
Active phase
Power-down phase
Oscillator restart phase
Active phase
2. Generate a reset. - A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-Down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT89C51RE2 and vectors the CPU to address 0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated the Power-Down mode should not write to a Port pin or to the external RAM. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM content.
Note:
Note:
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Table 88. Pin Conditions in Special Operating Modes
Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PSEN#
Reset Idle (internal code) Idle (external code) Power-Down (internal code) Power-Down (external code)
Floating Data
High Data
High Data
High Data
High Data
High High
High High
Floating
Data
Data
Data
Data
High
High
Data
Data
Data
Data
Data
Low
Low
Floating
Data
Data
Data
Data
Low
Low
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Registers
Table 89. PCON Register PCON (87:h) Power configuration Register
7 6 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL
SMOD1
SMOD0
Bit Mnemonic
Bit Number
Description Serial Port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial Port Mode bit 0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register.
7
SMOD1
6
SMOD0
5
-
reserved
Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General Purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. General Purpose flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. Power-Down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value= XXXX 0000b
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Oscillator
Registers
To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals. Table 90. CKRL Register CKRL - Clock Reload Register (97h)
7 6 5 4 3 2 1 0
CKRL7
Bit Number
CKRL6
CKRL5
CKRL4
Description
CKRL3
CKRL2
CKRL1
CKRL0
Mnemonic
7:0
CKRL
Clock Reload Register
Prescaler value
Reset Value = 1111 1111b Not bit addressable Table 91. PCON Register PCON - Power Control Register (87h)
7 6 5 4 3 2 1 0
SMOD1
Bit Number
SMOD0
-
POF
Description
GF1
GF0
PD
IDL
Bit Mnemonic
7
SMOD1
Serial Port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial Port Mode bit 0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-off Flag Cleared by software to recognize the next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General-purpose Flag Cleared by software for general-purpose usage. Set by software for general-purpose usage. General-purpose Flag Cleared by software for general-purpose usage. Set by software for general-purpose usage. Power-down Mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle Mode bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode.
6
SMOD0
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 00X1 0000b Not bit addressable
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Functional Block Diagram
Figure 46. Functional Oscillator Block Diagram
Reset CKRL Xtal1 Osc Xtal2 :2 FOSC 1 0 8-bit Prescaler-Divider 1 X2 CLK Periph CLK CPU Peripheral Clock CPU Clock Reload
CKCON0
0
Idle
CKRL = 0xFF?
Prescaler Divider
*
A hardware RESET puts the prescaler divider in the following state: * CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)
*
Any value between FFh down to 00h can be written by software into CKRL register in order to divide frequency of the selected oscillator: * CKRL = 00h: minimum frequency FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode) CKRL = FFh: maximum frequency FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
*
FCLK CPU and FCLK PERIPH In X2 Mode, for CKRL<>0xFF: F OSC F CPU = F CLKPERIPH = ---------------------------------------------In X1 Mode, for CKRL<>0xFF then: F OSC F CPU = F CLKPERIPH = ----------------------------------------------
2 x ( 255 - CKRL )
4 x ( 255 - CKRL )
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Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where TCLK PERIPH= 1/FCLK PERIPH. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16ms to 2s @ FOSCA = 12MHz. To manage this feature, refer to WDTPRG register description, Table 92. Table 92. WDTRST Register WDTRST - Watchdog Reset Register (0A6h)
7 6 5 4 3 2 1 0 -
Using the WDT
Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
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Table 93. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h)
7 Bit Number 6 Bit Mnemonic Description 5 4 3 2 S2 1 S1 0 S0
7 6 5 4 3 2 1 0
S2 S1 S0
WDT Time-out select bit 2 WDT Time-out select bit 1 WDT Time-out select bit 0 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Selected Time-out (214 - 1) machine cycles, 16. 3 ms @ FOSCA =12 MHz (215 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz (216 - 1) machine cycles, 65. 5 ms @ FOSCA=12 MHz (217 - 1) machine cycles, 131 ms @ FOSCA=12 MHz (218 - 1) machine cycles, 262 ms @ FOSCA=12 MHz (219 - 1) machine cycles, 542 ms @ FOSCA=12 MHz (220 - 1) machine cycles, 1.05 s @ FOSCA=12 MHz (221 - 1) machine cycles, 2.09 s @ FOSCA=12 MHz Reserved The value read from this bit is undetermined. Do not try to set this bit.
Reset value = XXXX X000
WDT During Power In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of exiting Power Down and Idle
Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the AT89C51RE2 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is better to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51RE2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
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Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 94. AUXR Register AUXR - Auxiliary Register (8Eh)
7 Bit Number 6 Bit Mnemonic Description Reserved 5 M0 4 XRS2 3 XRS1 2 XRS0 1 EXTRAM 0 AO
7
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
6
-
The value read from this bit is indeterminate. Do not set this bit.
Pulse length
5
M0
Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock periods.
4 3
XRS2 XRS1
XRAM Size
XRS2 0 0 0 0 1
XRS1 0 0 1 1 0
XRS0 XRAM size 0 256 bytes 1 0 1 0 512 bytes 768 bytes(default) 1024 bytes 1792 bytes
2
XRS0
EXTRAM bit Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
1
EXTRAM
Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected.
ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used.
0
AO
Reset Value = XX00 10'HSB. XRAM'0b Not bit addressable
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AT89C51RE2
Keyboard Interface
The AT89C51RE2 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power down modes. The keyboard interface interfaces with the C51 core through 3 special function registers: KBLS, the Keyboard Level Selection register (Table 97), KBE, The Keyboard interrupt Enable register (Table 96), and KBF, the Keyboard Flag register (Table 95). Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard interrupt (see Figure 47). As detailed in Figure 48 each keyboard input has the capability to detect a programmable level according to KBLS. x bit value. Level detection is then reported in interrupt flags KBF. x that can be masked by software using KBE. x bits. This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage of P1 inputs for other purpose. Figure 47. Keyboard Interface Block Diagram
Vcc
0
P1:x
1
Internal Pullup
KBF. x KBE. x KBLS. x
Figure 48. Keyboard Input Circuitry
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
Input Circuitry Input Circuitry Input Circuitry Input Circuitry KBDIT Input Circuitry Input Circuitry Input Circuitry Input Circuitry KBD IE1 Keyboard Interface Interrupt Request
Power Reduction Mode
P1 inputs allow exit from idle and power down modes as detailed in Section "Power Management", page 118.
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Registers
Table 95. KBF Register KBF-Keyboard Flag Register (9Eh)
7 KBF7 6 KBF6 Bit Mnemonic 5 KBF5 4 KBF4 3 KBF3 2 KBF2 1 KBF1 0 KBF0
Bit Number
Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set. Must be cleared by software. Keyboard line 6 flag Set by hardware when the Port line 6 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 6 bit in KBIE register is set. Must be cleared by software. Keyboard line 5 flag Set by hardware when the Port line 5 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 5 bit in KBIE register is set. Must be cleared by software. Keyboard line 4 flag Set by hardware when the Port line 4 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 4 bit in KBIE register is set. Must be cleared by software. Keyboard line 3 flag Set by hardware when the Port line 3 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 3 bit in KBIE register is set. Must be cleared by software. Keyboard line 2 flag Set by hardware when the Port line 2 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 2 bit in KBIE register is set. Must be cleared by software. Keyboard line 1 flag Set by hardware when the Port line 1 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 1 bit in KBIE register is set. Must be cleared by software. Keyboard line 0 flag Set by hardware when the Port line 0 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set. Must be cleared by software.
7
KBF7
6
KBF6
5
KBF5
4
KBF4
3
KBF3
2
KBF2
1
KBF1
0
KBF0
Reset Value= 0000 0000b
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Table 96. KBE Register KBE-Keyboard Input Enable Register (9Dh)
7 KBE7 Bit Number 6 KBE6 Bit Mnemonic 5 KBE5 4 KBE4 3 KBE3 2 KBE2 1 KBE1 0 KBE0
Description Keyboard line 7 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 7 bit in KBF register to generate an interrupt request. Keyboard line 6 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 6 bit in KBF register to generate an interrupt request. Keyboard line 5 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 5 bit in KBF register to generate an interrupt request. Keyboard line 4 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 4 bit in KBF register to generate an interrupt request. Keyboard line 3 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 3 bit in KBF register to generate an interrupt request. Keyboard line 2 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 2 bit in KBF register to generate an interrupt request. Keyboard line 1 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 1 bit in KBF register to generate an interrupt request. Keyboard line 0 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 0 bit in KBF register to generate an interrupt request.
7
KBE7
6
KBE6
5
KBE5
4
KBE4
3
KBE3
2
KBE2
1
KBE1
0
KBE0
Reset Value= 0000 0000b
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Table 97. KBLS Register KBLS-Keyboard Level Selector Register (9Ch)
7 KBLS7 6 KBLS6 Bit Mnemonic 5 KBLS5 4 KBLS4 3 KBLS3 2 KBLS2 1 KBLS1 0 KBLS0
Bit Number
Description Keyboard line 7 Level Selection bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. Keyboard line 6 Level Selection bit Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6. Keyboard line 5 Level Selection bit Cleared to enable a low level detection on Port line 5. Set to enable a high level detection on Port line 5. Keyboard line 4 Level Selection bit Cleared to enable a low level detection on Port line 4. Set to enable a high level detection on Port line 4. Keyboard line 3 Level Selection bit Cleared to enable a low level detection on Port line 3. Set to enable a high level detection on Port line 3. Keyboard line 2 Level Selection bit Cleared to enable a low level detection on Port line 2. Set to enable a high level detection on Port line 2. Keyboard line 1 Level Selection bit Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard line 0 Level Selection bit Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0.
7
KBLS7
6
KBLS6
5
KBLS5
4
KBLS4
3
KBLS3
2
KBLS2
1
KBLS1
0
KBLS0
Reset Value= 0000 0000b
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AT89C51RE2
2-wire Interface (TWI)
This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial communication standard. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The serial data transfer is limited to 400 Kbit/s in standard mode. Various communication configuration can be designed using this bus. Figure 49 shows a typical 2-wire bus configuration. All the devices connected to the bus can be master and slave.
Figure 49. 2-wire Bus Configuration
device1
device2
device3
...
deviceN
SCL SDA
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Figure 50. Block Diagram
8
SSADR
Address Register
Input Filter SDA
PI2.1
Comparator
Output Stage
SSDAT
Shift Register
ACK
8
Input Filter SCL
PI2.0
Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow
SSCON FCLK PERIPH/4
Output Stage
Interrupt
Control Register
7
Status Bits
Status Decoder
SSCS
Status Register
8
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Internal Bus
AT89C51RE2
Description
The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the Synchronous Serial Control register (SSCON; Table 107), the Synchronous Serial Data register (SSDAT; Table 108), the Synchronous Serial Control and Status register (SSCS; Table 109) and the Synchronous Serial Address register (SSADR Table 112). SSCON is used to enable the TWI interface, to program the bit rate (see Table 100), to enable slave modes, to acknowledge or not a received data, to send a START or a STOP condition on the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI module. SSCS contains a status code which reflects the status of the 2-wire logic and the 2-wire bus. The three least significant bits are always zero. The five most significant bits contains the status code. There are 26 possible status codes. When SSCS contains F8h, no relevant state information is available and no serial interrupt is requested. A valid status code is available in SSCS one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software. to Table 106. give the status for the master modes and miscellaneous states. SSDAT contains a byte of serial data to be transmitted or a byte which has just been received. It is addressable while it is not in process of shifting a byte. This occurs when 2-wire logic is in a defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SI is set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always contains the last byte present on the bus. SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which the TWI module will respond when programmed as a slave transmitter or receiver. The LSB is used to enable general call address (00h) recognition. Figure 51 shows how a data transfer is accomplished on the 2-wire bus. Figure 51. Complete Data Transfer on 2-wire Bus
SDA
MSB
acknowledgement signal from receiver SCL S start condition 1 2 7 8 9 ACK 1 2 3-8
acknowledgement signal from receiver 9 ACK
clock line held low while interrupts are serviced
P stop condition
The four operating modes are: * * * * Master Transmitter Master Receiver Slave transmitter Slave receiver
Data transfer in each mode of operation is shown in Table to Table 106 and Figure 52. to Figure 55.. These figures contain the following abbreviations: S : START condition R : Read bit (high level at SDA)
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W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P : STOP condition In Figure 52 to Figure 55, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in SSCS. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. When the serial interrupt routine is entered, the status code in SSCS is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Table to Table 106. Master Transmitter Mode In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (Figure 52). Before the master transmitter mode can be entered, SSCON must be initialised as follows: Table 98. SSCON Initialization
CR2 SSIE STA STO SI AA CR1 CR0
bit rate
1
0
0
0
X
bit rate
bit rate
CR0, CR1 and CR2 define the internal serial bit rate if external bit rate generator is not used. SSIE must be set to enable TWI. STA, STO and SI must be cleared. The master transmitter mode may now be entered by setting the STA bit. The 2-wire logic will now test the 2-wire bus and generate a START condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI bit in SSCON) is set, and the status code in SSCS will be 08h. This status must be used to vector to an interrupt routine that loads SSDAT with the slave address and the data direction bit (SLA+W). When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, SI is set again and a number of status code in SSCS are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table . This scheme is repeated until a STOP condition is transmitted. SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may switch to the master receiver mode by loading SSDAT with SLA+R. Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmitter (Figure 53). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7-bit slave address and the data direction bit (SLA+R). The serial interrupt flag SI must then be cleared before the serial transfer can continue.
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When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, the serial interrupt flag is set again and a number of status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table . This scheme is repeated until a STOP condition is transmitted. SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may switch to the master transmitter mode by loading SSDAT with SLA+W. Slave Receiver Mode In the slave receiver mode, a number of data bytes are received from a master transmitter (Figure 54). To initiate the slave receiver mode, SSADR and SSCON must be loaded as follows: Table 99. SSADR: Slave Receiver Mode Initialization
A6 A5 A4 A3 A2 A1 A0 GC
own slave address
The upper 7 bits are the address to which the TWI module will respond when addressed by a master. If the LSB (GC) is set the TWI module will respond to the general call address (00h); otherwise it ignores the general call address. Table 100. SSCON: Slave Receiver Mode Initialization
CR2 SSIE STA STO SI AA CR1 CR0
bit rate
1
0
0
0
1
bit rate
bit rate
CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable the TWI. The AA bit must be set to enable the own slave address or the general call address acknowledgement. STA, STO and SI must be cleared. When SSADR and SSCON have been initialised, the TWI module waits until it is addressed by its own slave address followed by the data direction bit which must be at logic 0 (W) for the TWI to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS. This status code is used to vector to an interrupt service routine.The appropriate action to be taken for each of these status code is detailed in Table . The slave receiver mode may also be entered if arbitration is lost while TWI is in the master mode (states 68h and 78h). If the AA bit is reset during a transfer, TWI module will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, the TWI module does not respond to its own slave address. However, the 2-wire bus is still monitored and address recognition may be resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate the module from the 2-wire bus. Slave Transmitter Mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 55). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the TWI module waits until it is addressed by
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its own slave address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS. This status code is used to vector to an interrupt service routine. The appropriate action to be taken for each of these status code is detailed in Table . The slave transmitter mode may also be entered if arbitration is lost while the TWI module is in the master mode. If the AA bit is reset during a transfer, the TWI module will transmit the last byte of the transfer and enter state C0h or C8h. the TWI module is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1's as serial data. While AA is reset, the TWI module does not respond to its own slave address. However, the 2-wire bus is still monitored and address recognition may be resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate the TWI module from the 2-wire bus. Miscellaneous States There are two SSCS codes that do not correspond to a define TWI hardware state (Table 106 ). These codes are discuss hereafter. Status F8h indicates that no relevant information is available because the serial interrupt flag is not set yet. This occurs between other states and when the TWI module is not involved in a serial transfer. Status 00h indicates that a bus error has occurred during a TWI serial transfer. A bus error is caused when a START or a STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions happen during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To recover from a bus error, the STO flag must be set and SI must be cleared. This causes the TWI module to enter the not addressed slave mode and to clear the STO flag (no other bits in SSCON are affected). The SDA and SCL lines are released and no STOP condition is transmitted.
Notes
the TWI module interfaces to the external 2-wire bus via two port pins: SCL (serial clock line) and SDA (serial data line). To avoid low level asserting on these lines when the TWI module is enabled, the output latches of SDA and SLC must be set to logic 1. Table 101. Bit Frequency Configuration
Bit Frequency ( kHz) CR2 CR1 CR0 FOSCA= 12 MHz FOSCA = 16 MHz FOSCA divided by
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
47 53.5 62.5 75 100 200 0.5 <. < 62.5
62.5 71.5 83 100 133.3 266.6 0.67 <. < 83
256 224 192 160 Unused 120 60 96 * (256 - reload valueTimer 1) (reload value range: 0-254 in mode 2)
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Figure 52. Format and State in the Master Transmitter Mode MT
Successfull transmission to a slave receiver
S
SLA
W
A
Data
A
P
08h
Next transfer started with a repeated start condition
18h
28h
S
SLA
W
10h
Not acknowledge received after the slave address
A
P
R
20h
Not acknowledge received after a data byte
MR A P
30h
Arbitration lost in slave address or data byte
A or A
Other master continues
A or A
Other master continues
38h
Arbitration lost and addressed as slave
38h
Other master continues
A
68h
78h
B0h
To corresponding states in slave mode
From master to slave From slave to master
Data n
A
Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus
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Table 102. Status in Master Transmitter Mode
Application software response Status Code SSSTA Status of the Twowire Bus and Twowire Hardware To SSCON To/From SSDAT SSSTA SSSTO SSI SSAA Next Action Taken by Two-wire Hardware
08h
A START condition has Write SLA+W been transmitted A repeated START condition has been transmitted Write SLA+W Write SLA+R
X
0
0
X
SLA+W will be transmitted. SLA+W will be transmitted. SLA+R will be transmitted. Logic will switch to master receiver mode Data byte will be transmitted. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data byte will be transmitted. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data byte will be transmitted. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data byte will be transmitted. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Two-wire bus will be released and not addressed slave mode will be entered. A START condition will be transmitted when the bus becomes free.
X X
0 0
0 0
X X
10h
Write data byte 18h SLA+W has been transmitted; ACK has been received No SSDAT action No SSDAT action No SSDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
Write data byte 20h SLA+W has been transmitted; NOT ACK has been received No SSDAT action No SSDAT action No SSDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
Write data byte 28h Data byte has been transmitted; ACK has been received No SSDAT action No SSDAT action No SSDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
Write data byte 30h Data byte has been transmitted; NOT ACK has been received No SSDAT action No SSDAT action No SSDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
38h
Arbitration lost in SLA+W or data bytes
No SSDAT action No SSDAT action
0 1
0 0
0 0
X X
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Figure 53. Format and State in the Master Receiver Mode MR
Successfull transmission to a slave receiver
S
SLA
R
A
Data
A
Data
A
P
08h
Next transfer started with a repeated start condition
40h
50h
58h
S
SLA
R
10h
Not acknowledge received after the slave address
A
P
W
48h
MT
Arbitration lost in slave address or acknowledge bit
A or A
Other master continues
A
Other master continues
38h
Arbitration lost and addressed as slave
38h
Other master continues
A
68h
78h
B0h
To corresponding states in slave mode
From master to slave From slave to master
Data n
A
Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus
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Table 103. Status in Master Receiver Mode
Application software response Status Code SSSTA Status of the Twowire Bus and Twowire Hardware To SSCON To/From SSDAT SSSTA SSSTO SSI SSAA Next Action Taken by Two-wire Hardware
08h
A START condition has Write SLA+R been transmitted A repeated START condition has been transmitted Write SLA+R Write SLA+W
X
0
0
X
SLA+R will be transmitted. SLA+R will be transmitted. SLA+W will be transmitted. Logic will switch to master transmitter mode. Two-wire bus will be released and not addressed slave mode will be entered. A START condition will be transmitted when the bus becomes free. Data byte will be received and NOT ACK will be returned. Data byte will be received and ACK will be returned. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data byte will be received and NOT ACK will be returned. Data byte will be received and ACK will be returned. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset.
X X
0 0
0 0
X X
10h
38h
Arbitration lost in SLA+R or NOT ACK bit SLA+R has been transmitted; ACK has been received
No SSDAT action No SSDAT action No SSDAT action No SSDAT action No SSDAT action No SSDAT action No SSDAT action Read data byte Read data byte Read data byte Read data byte Read data byte
0 1 0 0 1 0 1 0 0 1 0 1
0 0 0 0 0 1 1 0 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0
X X 0 1 X X X 0 1 X X X
40h
48h
SLA+R has been transmitted; NOT ACK has been received
50h
Data byte has been received; ACK has been returned
58h
Data byte has been received; NOT ACK has been returned
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Figure 54. Format and State in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged. S SLA W A Data A Data A P or S
60h
80h
80h
A0h
Last data byte received is not acknowledged.
A
P or S
88h Arbitration lost as master and addressed as slave A
68h
Reception of the general call address and one or more data bytes.
General Call
A
Data
A
Data
A
P or S
70h Last data byte received is not acknowledged.
90h
90h
A0h
A
P or S
98h Arbitration lost as master and addressed as slave by general call A
78h
From master to slave From slave to master
Data n
A
Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus
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Table 104. Status in Slave Receiver Mode
Application Software Response Status Code (SSCS) To/from SSDAT Status of the 2-wire bus and 2-wire hardware STA To SSCON STO SI AA Next Action Taken By 2-wire Software
60h
Own SLA+W has been received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+W has been received; ACK has been returned General call address has been received; ACK has been returned Arbitration lost in SLA+R/W as master; general call address has been received; ACK has been returned Previously addressed with own SLA+W; data has been received; ACK has been returned
No SSDAT action or No SSDAT action
X X
0 0
0 0
0 1
Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned
No SSDAT action or No SSDAT action
X X
0 0
0 0
0 1
68h
No SSDAT action or No SSDAT action
X X
0 0
0 0
0 1
70h
No SSDAT action or No SSDAT action
X X
0 0
0 0
0 1
78h
No SSDAT action or No SSDAT action
X X
0 0
0 0
0 1
80h
Read data byte or Read data byte or 88h Previously addressed with own SLA+W; data has been received; NOT ACK has been returned
0 0
0 0
0 0
0 1
Read data byte or
1
0
0
0
Read data byte
1
0
0
1
90h
Previously addressed with general call; data has been received; ACK has been returned
Read data byte or Read data byte
X X
0 0
0 0
0 1
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Table 104. Status in Slave Receiver Mode (Continued)
Application Software Response Status Code (SSCS) To/from SSDAT Status of the 2-wire bus and 2-wire hardware STA To SSCON STO SI AA Next Action Taken By 2-wire Software
Read data byte or Read data byte or 98h Previously addressed with general call; data has been received; NOT ACK has been returned
0 0
0 0
0 0
0 1
Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free
Read data byte or
1
0
0
0
Read data byte
1
0
0
1
No SSDAT action or No SSDAT action or A0h A STOP condition or repeated START condition has been received while still addressed as slave
0 0
0 0
0 0
0 1
No SSDAT action or
1
0
0
0
No SSDAT action
1
0
0
1
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Figure 55. Format and State in the Slave Transmitter Mode Reception of the S own slave address and one or more data bytes SLA R A Data A Data A P or S
A8h
B8h
C0h
Arbitration lost as master and addressed as slave
A
B0h
Last data byte transmitted. Switched to not addressed slave (AA=0)
A
All 1's P or S
C8h
From master to slave From slave to master
Data n
A
Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus
Table 105. Status in Slave Transmitter Mode
Application Software Response Status Code (SSCS) To/from SSDAT Status of the 2-wire bus and 2-wire hardware STA To SSCON STO SI AA Next Action Taken By 2-wire Software
A8h
Own SLA+R has been received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+R has been received; ACK has been returned Data byte in SSDAT has been transmitted; NOT ACK has been received
Load data byte or Load data byte
X X
0 0
0 0
0 1
Last data byte will be transmitted and NOT ACK will be received Data byte will be transmitted and ACK will be received Last data byte will be transmitted and NOT ACK will be received Data byte will be transmitted and ACK will be received Last data byte will be transmitted and NOT ACK will be received Data byte will be transmitted and ACK will be received
Load data byte or Load data byte
X X
0 0
0 0
0 1
B0h
Load data byte or Load data byte
X X
0 0
0 0
0 1
B8h
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Table 105. Status in Slave Transmitter Mode (Continued)
Application Software Response Status Code (SSCS) To/from SSDAT Status of the 2-wire bus and 2-wire hardware STA To SSCON STO SI AA Next Action Taken By 2-wire Software
No SSDAT action or No SSDAT action or C0h Data byte in SSDAT has been transmitted; NOT ACK has been received
0 0
0 0
0 0
0 1
Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free
No SSDAT action or
1
0
0
0
No SSDAT action
1
0
0
1
No SSDAT action or No SSDAT action or C8h Last data byte in SSDAT has been transmitted (AA=0); ACK has been received
0 0
0 0
0 0
0 1
No SSDAT action or
1
0
0
0
No SSDAT action
1
0
0
1
Table 106. Miscellaneous Status
Application Software Response To/from SSDAT STA To SSCON Next Action Taken By 2-wire AA Software
Status Code (SSCS)
Status of the 2-wire bus and 2-wire hardware
STO
SI
F8h
No relevant state information available; SI= 0
No SSDAT action
No SSCON action
Wait or proceed current transfer
00h
Bus error due to an illegal START or STOP condition
No SSDAT action
0
1
0
X
Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and STO is reset.
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Registers
Table 107. SSCON Register SSCON - Synchronous Serial Control register (93h)
7 CR2
Bit Number
6 SSIE
5 STA
4 STO
3 SI
2 AA
1 CR1
0 CR0
Bit Mnemonic Description
7
CR2
Control Rate bit 2 See Table 101. Synchronous Serial Interface Enable bit Clear to disable the TWI module. Set to enable the TWI module. Start flag Set to send a START condition on the bus. Stop flag Set to send a STOP condition on the bus. Synchronous Serial Interrupt flag Set by hardware when a serial interrupt is requested. Must be cleared by software to acknowledge interrupt. Assert Acknowledge flag Clear in master and slave receiver modes, to force a not acknowledge (high level on SDA). Clear to disable SLA or GCA recognition. Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter modes. Set in master and slave receiver modes, to force an acknowledge (low level on SDA). This bit has no effect when in master transmitter mode. Control Rate bit 1 See Table 101. Control Rate bit 0 See Table 101.
6
SSIE
5
STA
4
ST0
3
SI
2
AA
1
CR1
0
CR0
Table 108. SSDAT (95h) - Syncrhonous Serial Data register (read/write)
SD7 7 SD6 6 SD5 5 SD4 4 SD3 3 SD2 2 SD1 1 SD0 0
Bit Number
Bit Mnemonic Description
7 6 5 4 3 2
SD7 SD6 SD5 SD4 SD3 SD2
Address bit 7 or Data bit 7. Address bit 6 or Data bit 6. Address bit 5 or Data bit 5. Address bit 4 or Data bit 4. Address bit 3 or Data bit 3. Address bit 2 or Data bit 2.
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Bit Number Bit Mnemonic Description
1 0
SD1 SD0
Address bit 1 or Data bit 1. Address bit 0 (R/W) or Data bit 0.
Table 109. SSCS (094h) read - Synchronous Serial Control and Status Register
7 SC4 6 SC3 5 SC2 4 SC1 3 SC0 2 0 1 0 0 0
Table 110. SSCS Register: Read Mode - Reset Value = F8h
Bit Number Bit Mnemonic Description
0 1 2 3
0 0 0 SC0
Always zero Always zero Always zero
Status Code bit 0 See to Table 106. Status Code bit 1
4
SC1
See to Table 106.
Status Code bit 2 See to Table 106. Status Code bit 3 See to Table 106. Status Code bit 4 See to Table 106.
5
SC2
6
SC3
7
SC4
Table 111. SSADR (096h) - Synchronus Serial Address Register (read/write)
7 A7 6 A6 5 A5 4 A4 3 A3 2 A2 1 A1 0 A0
Table 112. SSADR Register - Reset value = FEh
Bit Number Bit Mnemonic Description
7 6 5 4 3 2 1
A7 A6 A5 A4 A3 A2 A1
Slave Address bit 7 Slave Address bit 6 Slave Address bit 5 Slave Address bit 4 Slave Address bit 3 Slave Address bit 2 Slave Address bit 1
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Bit Number
Bit Mnemonic Description
General Call bit 0 GC Clear to disable the general call address recognition. Set to enable the general call address recognition.
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Serial Port Interface (SPI)
Features
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI Module include the following: * * * * * Full-duplex, three-wire synchronous transfers Master or Slave operation Six programmable Master clock rates in master mode Serial clock with programmable polarity and phase Master Mode fault error flag with MCU interrupt capability
Signal Description Figure 56 shows a typical SPI bus configuration using one Master controller and many Slave
peripherals. The bus is made of three wires connecting all the devices. Figure 56. SPI Master/Slaves Interconnection
MISO MOSI SCK SS
Slave 1
MISO MOSI SCK SS
VDD
Master
0 1 2 3
PORT
Slave 4
MISO MOSI SCK SS
Slave 3
MISO MOSI SCK SS
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices. Master Output Slave Input (MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This signal is used to synchronize the data transmission both in and out of the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines. Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port pins (Figure 57). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission.
Master Input Slave Output (MISO)
SPI Serial Clock (SCK)
Slave Select (SS)
MISO MOSI SCK SS
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In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. The SS pin could be used as a general-purpose if the following conditions are met: * The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration can be found when only one Master is driving the network and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in the SPSCR will never be set(1). The Device is configured as a Slave with CPHA and SSDIS control bits set(2). This kind of configuration can happen when the system includes one Master and one Slave only. Therefore, the device should always be selected and there is no reason that the Master uses the SS pin to select the communicating Slave device.
1. Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken not to set SSDIS control bit when CPHA ='0' because in this mode, the SS is used to start the transmission.
*
Note:
Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is selected from one of seven clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. Table 113 gives the different clock rates selected by SPR2:SPR1:SPR0. In Slave mode, the maximum baud rate allowed on the SCK input is limited to Fsys/4 Table 113. SPI Master Baud Rate Selection
SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Don't Use FCLK PERIPH /4 FCLK PERIPH/8 FCLK PERIPH /16 FCLK PERIPH /32 FCLK PERIPH /64 FCLK PERIPH /128 Don't Use
No BRG 4 8 16 32 64 128 No BRG
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Functional Description
Figure 57 shows a detailed structure of the SPI Module.
Figure 57. SPI Module Block Diagram
Internal Bus SPDAT Transmit Data Register Shift Register
7 6 5 4 3 2 1 0
Receive Data Register SPSCR
SPIF OVR MODF SPTE UARTM SPTEIE MODFIE
Pin Control Logic
MOSI MISO
SPI Control
Clock Logic
M S
SCK SS
SPCON
SPR2
SPEN SSDIS MSTR
CPOL
CPHA
SPR1
SPR0
FCLK PERIPH
SPI Interrupt Request
8-bit bus 1-bit signal
Operating Modes
The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode. The configuration and initialization of the SPI Module is made through two registers: * * * The Serial Peripheral Control register (SPCON) The Serial Peripheral Status and Control Register (SPSCR) The Serial Peripheral DATa register (SPDAT)
Once the SPI is configured, the data exchange is made using: During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
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When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 58). Figure 58. Full-Duplex Master-Slave Interconnection
MISO MOSI SPI Clock Generator SCK SS VDD MISO MOSI SCK SS VSS
8-bit Shift register
8-bit Shift register
Master MCU
Slave MCU
Master Mode
The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift register. The Byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another Byte shifts in from the Slave on the Master's MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSCR becomes set. At the same time that SPIF becomes set, the received Byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSCR) with the SPIF bit set, and then reading the SPDAT. The SPI operates in Slave mode when the Master bit, MSTR (2) , in the SPCON register is cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must be set to'0'. SS must remain low until the transmission is complete. In a Slave SPI Module, data enters the shift register under the control of the SCK from the Master SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another Byte enters the shift register (3). A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission.
Slave Mode
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock Polarity (CPOL (4)) and the Clock Phase (CPHA4). CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 59 and Figure 60). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
1. 2. 3. 4.
The SPI Module should be configured as a Master before it is enabled (SPEN set). Also, the Master SPI should be configured before the Slave SPI. The SPI Module should be configured as a Slave before it is enabled (SPEN set). The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN ='0').
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Figure 59. Data Transmission Format (CPHA = 0)
SCK Cycle Number SPEN (Internal)
1 2 3 4 5 6 7 8
SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point
MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB
Figure 60. Data Transmission Format (CPHA = 1)
SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point
MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB 1 2 3 4 5 6 7 8
Figure 61. CPHA/SS Timing
MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) Byte 1 Byte 2 Byte 3
As shown in Figure 59, the first SCK edge is the MSB capture strobe. Therefore, the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each Byte transmitted (Figure 61). Figure 60 shows an SPI transmission in which CPHA is'1'. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 61). This format may be preferred in systems having only one Master and only one Slave driving the MISO data line. Queuing transmission For an SPI configured in master or slave mode, a queued data byte must be transmitted/received immediately after the previous transmission has completed.
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When a transmission is in progress a new data can be queued and sent as soon as transmission has been completed. So it is possible to transmit bytes without latency, useful in some applications. The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that the user application can write SPDAT with the data to be transmitted until the SPTE becomes cleared. Figure 62 shows a queuing transmission in master mode. Once the Byte 1 is ready, it is immediately sent on the bus. Meanwhile an other byte is prepared (and the SPTE is cleared), it will be sent at the end of the current transmission. The next data must be ready before the end of the current transmission.
Figure 62. Queuing Transmission In Master Mode
SCK
MOSI MISO Data
MSB MSB
B6 B6
B5 B5
B4 B4
B3 B3
B2 B2
B1 B1
LSB MSB LSB MSB
B6 B6
B5 B5
B4 B4
B3 B3
B2 B2 Byte 3
B1 B1
LSB LSB
Byte 1
Byte 2
BYTE 1 under transmission
SPTE
BYTE 2 under transmission
In slave mode it is almost the same except it is the external master that start the transmission. Also, in slave mode, if no new data is ready, the last value received will be the next data byte transmitted.
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Error Conditions The following flags in the SPSCR register indicate the SPI error conditions:
Mode Fault Error (MODF)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. * Mode fault detection in Master mode:
MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: - - - An SPI receiver/error CPU interrupt request is generated The SPEN bit in SPCON is cleared. This disables the SPI The MSTR bit in SPCON is cleared
Clearing the MODF bit is accomplished by a read of SPSCR register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared. Figure 63. Mode Fault Conditions in Master Mode (Cpha ='1'/Cpol ='0')
SCK cycle # SCK (from master) MOSI (from master) MISO (from slave) SPI enable SS (master) SS (slave)
1 z 0 1 z 0 1 z 0 1 z 0 1 z 0 1 z 0
0
0
1
2
3
0
MSB MSB
B6 B6 B5
MODF detected
MODF detected
Note:
When SS is discarded (SS disabled) it is not possible to detect a MODF error in master mode because the SPI is internally unselected and the SS pin is a general purpose I/O.
*
Mode fault detection in Slave mode
In slave mode, the MODF error is detected when SS goes high during a transmission. A transmission begins when SS goes low and ends once the incoming SCK goes back to its idle level following the shift of the eighteen data bit. A MODF error occurs if a slave is selected (SS is low) and later unselected (SS is high) even if no SCK is sent to that slave. At any time, a'1' on the SS pin of a slave SPI puts the MISO pin in a high impedance state and internal state counter is cleared. Also, the slave SPI ignores all incoming SCK clocks, even if it was already in the middle of a transmission. A new transmission will be performed as soon as SS pin returns low.
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Figure 64. Mode Fault Conditions in Slave Mode
SCK cycle # SCK (from master) MOSI (from master) MISO (from slave) SS (slave)
1 z 0 1 z 0 1 z 0 1 z 0
0
0
1
2
3
4
MSB MSB MSB
B6 B6
B5
B4
MODF detected
MODF detected
Note:
when SS is discarded (SS disabled) it is not possible to detect a MODF error in slave mode because the SPI is internally selected. Also the SS pin becomes a general purpose I/O.
OverRun Condition
This error mean that the speed is not adapted for the running application: An OverRun condition occurs when a byte has been received whereas the previous one has not been read by the application yet. The last byte (which generate the overrun error) does not overwrite the unread data so that it can still be read. Therefore, an overrun error always indicates the loss of data.
Interrupts
Three SPI status flags can generate a CPU interrupt requests: Table 114. SPI Interrupts
Flag Request
SPIF (SPI data transfer) MODF (Mode Fault) SPTE (Transmit register empty)
SPI Transmitter Interrupt Request SPI mode-fault Interrupt Request SPI transmit register empty Interrupt Request
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt request only when SPTEIE is disabled. Mode Fault flag, MODF: This bit is set to indicate that the level on the SS is inconsistent with the mode of the SPI (in both master and slave modes). Serial Peripheral Transmit Register empty flag, SPTE: This bit is set when the transmit buffer is empty (other data can be loaded is SPDAT). SPTE bit generates transmitter CPU interrupt request only when SPTEIE is enabled. Note: While using SPTE interruption for "burst mode" transfers (SPTEIE='1'), the user software application should take care to clear SPTEIE, during the last but one data reception (to be able to generate an interrupt on SPIF flag at the end of the last data reception).
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Figure 65. SPI Interrupt Requests Generation
SPIF
SPTEIE SPTE
SPI CPU Interrupt Request
MODFIE MODF
Registers
Three registers in the SPI module provide control, status and data storage functions. These registers are describe in the following paragraphs. * * * * * * The Serial Peripheral Control Register does the following: Selects one of the Master clock rates Configure the SPI Module as Master or Slave Selects serial clock polarity and phase Enables the SPI Module Frees the SS pin for a general-purpose
Serial Peripheral Control Register (SPCON)
Table 115 describes this register and explains the use of each bit Table 115. SPCON Register SPCON - Serial Peripheral Control Register (0D4H)
7 SPR2 Bit Number 6 SPEN 5 SSDIS 4 MSTR Description Serial Peripheral Rate 2 3 CPOL 2 CPHA 1 SPR1 0 SPR0
Bit Mnemonic
7
SPR2
Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and SPR0 for detail).
Serial Peripheral Enable
6
SPEN
Cleared to disable the SPI interface (internal reset of the SPI). Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes. 5 SSDIS Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA ='0'. When SSDIS is set, no MODF interrupt request is generated.
Serial Peripheral Master
4
MSTR
Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master.
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Bit Number
Bit Mnemonic
Description Clock Polarity
3
CPOL
Cleared to have the SCK set to'0' in idle state. Set to have the SCK set to'1' in idle state.
Clock Phase
2
CPHA
Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL).
SPR2 SPR1 SPR0 Serial Peripheral Rate
1
SPR1
0 0 0 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Invalid FCLK PERIPH /4 FCLK PERIPH /8 FCLK PERIPH /16 FCLK PERIPH /32 FCLK PERIPH /64 FCLK PERIPH /128 Invalid
0
SPR0
1 1 1
Reset Value = 0001 0100b Not bit addressable Serial Peripheral Status Register and Control (SPSCR) The Serial Peripheral Status Register contains flags to signal the following conditions: * * * Data transfer complete Write collision Inconsistent logic level on SS pin (mode fault error)
Table 116. SPSCR Register SPSCR - Serial Peripheral Status and Control register (C4H)
7 SPIF 6 Bit Mnemonic 5 OVR 4 MODF 3 SPTE 2 UARTM 1 SPTEIE 0 MODFIE
Bit Number
Description Serial Peripheral Data Transfer Flag
7
SPIF
Cleared by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. This bit is cleared when reading or writing SPDATA after reading SPSCR.
6
-
Reserved The value read from this bit is indeterminate. Do not set this bit. Overrun Error Flag
5
OVR
- Set by hardware when a byte is received whereas SPIF is set (the previous received data is not overwritten). - Cleared by hardware when reading SPSCR
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Bit Number Bit Mnemonic Description Mode Fault
- Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master and slave modes). - Cleared by hardware when reading SPSCR 4 MODF When MODF error occurred: - In slave mode: SPI interface ignores all transmitted data while SS remains high. A new transmission is perform as soon as SS returns low. - In master mode: SPI interface is disabled (SPEN=0, see description for SPEN bit in SPCON register).
Serial Peripheral Transmit register Empty
3
SPTE
- Set by hardware when transmit register is empty (if needed, SPDAT can be loaded with another data). - Cleared by hardware when transmit register is full (no more data should be loaded in SPDAT).
Serial Peripheral UART mode
2
UARTM
Set and cleared by software: - Clear: Normal mode, data are transmitted MSB first (default) - Set: UART mode, data are transmitted LSB first.
Interrupt Enable for SPTE
Set and cleared by software: 1 SPTEIE - Set to enable SPTE interrupt generation (when SPTE goes high, an interrupt is generated). - Clear to disable SPTE interrupt generation Caution: When SPTEIE is set no interrupt generation occurred when SPIF flag goes high. To enable SPIF interrupt again, SPTEIE should be cleared.
Interrupt Enable for MODF
0
MODFIE
Set and cleared by software: - Set to enable MODF interrupt generation - Clear to disable MODF interrupt generation
Reset Value = 00X0 XXXXb Not Bit addressable
Serial Peripheral DATa Register (SPDAT)
The Serial Peripheral Data Register (Table 117) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model. A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register. Table 117. SPDAT Register SPDAT - Serial Peripheral Data Register (C5H)
7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0
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SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no ongoing exchange. However, special care should be taken when writing to them while a transmission is on-going: * * * * * Do not change SPR2, SPR1 and SPR0 Do not change CPHA and CPOL Do not change MSTR Clearing SPEN would immediately disable the peripheral Writing to the SPDAT will cause an overflow.
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Power Monitor
The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51RE2 is powered up.
Description
In order to startup and maintain the microcontroller in correct operating mode, VCC has to be stabilized in the VCC operating range and the oscillator has to be stabilized with a nominal amplitude compatible with logic level VIH/VIL. These parameters are controlled during the three phases: power-up, normal operation and power going down. See Figure 66. Figure 66. Power Monitor Block Diagram
VCC
CPU core
Power On Reset Power Fail Detect Voltage Regulator
Regulated Supply
Memories
Peripherals
XTAL1
(1)
Internal Reset
RST pin
PCA Watchdog
Hardware Watchdog
Note:
1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail Detect threshold level, the Reset will be applied immediately.
The Voltage regulator generates a regulated internal supply for the CPU core the memories and the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator.
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The Power fail detect monitor the supply generated by the voltage regulator and generate a reset if this supply falls below a safety threshold as illustrated in the Figure 67 below. Figure 67. Power Fail Detect Vcc
t
Reset
Vcc
When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted. If the internal power supply falls below a safety level, a reset is immediately asserted.
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Power-off Flag
The power-off flag allows the user to distinguish between a "cold start" reset and a "warm start" reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (Table 118). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of reset. Table 118. PCON Register PCON - Power Control Register (87h)
7 SMOD1 Bit Number 6 SMOD0 Bit Mnemonic Description Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL
7
SMOD1
6
SMOD0
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 00X1 0000b Not bit addressable
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Reset
Introduction
The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 68. Reset schematic
Power Monitor Hardware Watchdog PCA Watchdog Internal Reset
RST
Reset Input
The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V CC as shown in Figure 69. Resistor value and input characteristics are discussed in the Section "DC Characteristics" of the AT89C51RE2 datasheet. Figure 69. Reset Circuitry and Power-On Reset
VDD
RST
R
To internal reset
+
RST
RST
VSS
a. RST input circuitry
b. Power-on Reset
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Reset Output
As detailed in Section "Hardware Watchdog Timer", page 124, the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 k resistor must be added as shown Figure 70. Figure 70. Recommended Reset Output Schematic
VDD
+
RST
VDD
1K
RST
VSS
To other on-board circuitry
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Electrical Characteristics
Absolute Maximum Ratings
Note: I = industrial ........................................................-40C to 85C Storage Temperature .................................... -65C to + 150C Voltage on VCC to VSS (standard voltage) .........-0.5V to + 6.5V Voltage on VCC to VSS (low voltage)..................-0.5V to + 4.5V Voltage on Any Pin to VSS ..........................-0.5V to VCC + 0.5V Power Dissipation ........................................................... 1 W(2) Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power dissipation is based on the maximum allowable die temperature and the thermal resistance of the package.
DC Parameters
TA = -40C to +85C; VSS = 0V; VCC =2.7V to 5.5V; F = 0 to 40 MHz
Symbol Parameter Min Typ Max Unit Test Conditions
VIL VIH VIH1
Input Low Voltage Input High Voltage except RST, XTAL1 Input High Voltage RST, XTAL1
-0.5 0.2 VCC + 0.9 0.7 VCC
0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5
V V V VCC = 4.5V to 5.5V
0.3 0.45 VOL Output Low Voltage, ports 1, 2, 3, 4 (6) 1.0
V V V
IOL = 100 A(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) VCC = 2.7V to 5.5V IOL = 0.8 mA(4) VCC = 4.5V to 5.5V IOL = 200 A(4) IOL = 3.2 mA(4) IOL = 7.0 mA(4) VCC = 2.7V to 5.5V IOL = 1.6 mA(4) VCC = 5V 10% IOH = -10 A IOH = -30 A IOH = -60 A
0.45
V
0.3 0.45 VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 1.0
V V V
0.45
V
VCC - 0.3 VCC - 0.7 VOH Output High Voltage, ports 1, 2, 3, 4 VCC - 1.5
V V V
VCC = 2.7V to 5.5V 0.9 VCC V IOH = -10 A VCC = 5V 10% VCC - 0.3 VCC - 0.7 VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 1.5 V V V IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA
VCC = 2.7V to 5.5V 0.9 VCC V IOH = -10 A
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TA = -40C to +85C; VSS = 0V; VCC =2.7V to 5.5V; F = 0 to 40 MHz (Continued)
Symbol Parameter Min Typ Max Unit Test Conditions
RRST IIL ILI ITL CIO IPD ICCOP ICCIDLE ICCWRITE tWRITE
RST Pull-down Resistor Logical 0 Input Current ports 1, 2, 3, 4 and 5 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 Capacitance of I/O Buffer Power-down Current Power Supply Current on normal mode Power Supply Current on idle mode Power Supply Current on flash write Flash programming time
50
200(5)
250 -50
10
k
A A A
VIN = 0.45V 0.45V < VIN < VCC VIN = 2.0V FC = 3 MHz TA = 25C 2.7 < VCC < 5.5V(3) VCC = 5.5V(1) VCC = 5.5V(2) VCC = 5.5V 2.7 < VCC < 5.5V
-650 10 75 150 0.4 x Frequency (MHz) + 5 0.3 x Frequency (MHz) + 5 0.8 x Frequency (MHz) + 15 7 10
pF
A
mA mA mA ms
Notes:
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 74), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 71). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 72). 3. Power-down ICC is measured with all output pins disconnected; EA = VCC, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 73). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
Figure 71. ICC Test Condition, Active Mode
VCC ICC VCC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC
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Figure 72. ICC Test Condition, Idle Mode
VCC ICC VCC P0 RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC
Figure 73. ICC Test Condition, Power-down Mode
VCC ICC VCC P0 RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC
Figure 74. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1
AC Parameters
Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. (Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF.) Table 119 Table 122, and Table 125 give the description of each AC symbols. Table 120, Table 121, Table 123 and Table 126 gives the range for each AC parameter. Table 120, Table 121 and Table 127 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. Take the x value in the corresponding column (-M or -L) and use this value in the formula.
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Example: TLLIU for -M and 20 MHz, Standard clock. x = 35 ns T 50 ns TCCIV = 4T - x = 165 ns External Program Memory Characteristics Table 119. Symbol Description
Symbol Parameter
T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ
Oscillator clock period ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instruction In PSEN Low to Address Float
Table 120. AC Parameters for a Fix Clock
Symbol Min -M(1) Max Min -L(2) Max Units
T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ
25 35 5 5 n 65 5 50 30 0 10 80 10
25 35 5 5 65 5 50 30 0 10 80 10
ns ns ns ns ns ns ns ns ns ns ns ns
Notes:
1. ` -L ` refers to 2V - 5.5V version. 2. ` -M ' refers to 4.5V to 5.5V version.
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Table 121. AC Parameters for a Variable Clock
Symbol Type Standard Clock X2 Clock X parameter for -M(1) range X parameter for -L(2) range Units
TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ
Min Min Min Max Min Min Max Min Max Max Max
2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x
T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x
15 20 20 35 15 25 45 0 15 45 10
15 20 20 35 15 25 45 0 15 45 10
ns ns ns ns ns ns ns ns ns ns ns
Notes:
1. ` -L ` refers to 2V - 5.5V version. 2. ` -M ' refers to 4.5V to 5.5V version.
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External Program Memory Read Cycle
12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ
External Data Memory Characteristics
Table 122. Symbol Description
Symbol Parameter
TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH
RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data Set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high
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Table 123. AC Parameters for a Fix Clock
-M(1) Symbol Min Max Min -L(2) Max Units
TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH
125 125 95 0 25 155 160 45 70 5 155 10 0 5 45 105
125 125 95 0 25 155 160 45 70 5 155 10 0 5 45 105
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes:
1. ` -L ` refers to 2V - 5.5V version. 2. ` -M ' refers to 4.5V to 5.5V version.
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Table 124. AC Parameters for a Variable Clock
Symbol Type Standard Clock X2 Clock X parameter for -M(1) range X parameter for -L(2) range Units
TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH
Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max
6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x
3T-x 3T-x 2.5 T - x x T-x 4T -x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x
25 25 30 0 25 45 65 30 30 30 20 20 15 0 20 20
25 25 30 0 25 45 65 30 30 30 20 20 15 0 20 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes:
1. ` -L ` refers to 2V - 5.5V version. 2. ` -M ' refers to 4.5V to 5.5V version.
External Data Memory Write Cycle
ALE TWHLH
PSEN
TLLWL
TWLWH
WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX
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External Data Memory Read Cycle
ALE TLLDV TWHLH
PSEN
TLLWL
TRLRH TRHDZ TRHDX DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2
RD TAVDV TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2
Serial Port Timing Shift Register Mode
Table 125. Symbol Description
Symbol Parameter
TXLXL TQVHX TXHQX TXHDX TXHDV
Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
Table 126. AC Parameters for a Fix Clock
-M(1) Symbol Min Max Min -L(2) Max Units
TXLXL TQVHX TXHQX TXHDX TXHDV
300 200 30 0 117
300 200 30 0 117
ns ns ns ns ns
Notes:
1. ` -L ` refers to 2V - 5.5V version. 2. ` -M ' refers to 4.5V to 5.5V version.
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Table 127. AC Parameters for a Variable Clock
Symbol Type Standard Clock X2 Clock X Parameter For -M(1) Range X Parameter For -L(2) Range Units
TXLXL TQVHX TXHQX TXHDX TXHDV
Min Min Min Min Max
12 T 10 T - x 2T-x x 10 T - x
6T 5T-x T-x x 5 T- x 50 20 0 133 50 20 0 133
ns ns ns ns ns
Notes:
1. ` -L ` refers to 2V - 5.5V version. 2. ` -M ' refers to 4.5V to 5.5V version.
Shift Register Timing Waveforms
INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV
VALID VALID
0
1
2
3
4
5
6
7
8
TXHQX 1 2 TXHDX
VALID VALID VALID VALID VALID
3
4
5
6
7 SET TI
VALID
SET RI
External Clock Drive Waveforms
VCC-0.5V 0.45V
0.7VCC 0.2VCC-0.1 TCHCL TCLCX TCLCL TCHCX TCLCH
AC Testing Input/Output Waveforms
VCC -0.5V INPUT/OUTPUT 0.45V
0.2 VCC + 0.9 0.2 VCC - 0.1
AC inputs during testing are driven at VCC - 0.5 for a logic "1" and 0.45V for a logic "0". Timing measurement are made at VIH min. for a logic "1" and VIL max for a logic "0". Float Waveforms
FLOAT VOH - 0.1V VOL + 0.1V VLOAD VLOAD + 0.1V VLOAD - 0.1V
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For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
Figure 75. Internal Clock Signals INTERNAL
CLOCK XTAL2 ALE
EXTERNAL PROGRAM MEMORY FETCH
STATE4 P1 P2
STATE5 P1 P2
STATE6 P1 P2
STATE1 P1 P2
STATE2 P1 P2
STATE3 P1 P2
STATE4 P1 P2
STATE5 P1 P2
THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION
PSEN P0 DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT
P2 (EXT)
READ CYCLE RD
INDICATES ADDRESS TRANSITIONS
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
DATA SAMPLED FLOAT
P2
WRITE CYCLE
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WR P0
DPL OR Rt OUT DATA OUT P2
PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED
RXD SAMPLED
RXD SAMPLED
TXD (MODE 0)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 176
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Flash Memory Table 128. Timing Symbol Definitions
Signals Conditions
S (Hardware condition) R B
PSEN#,EA RST FBUSY flag
L V X
Low Valid No Longer Valid
Table 129. Memory AC Timing VDD = 3V to 5.5V, TA = -40 to +85C
Symbol Parameter Min Typ Max Unit
TSVRL TRLSX TBHBL NFCY TFDR
Input PSEN# Valid to RST Edge Input PSEN# Hold after RST Edge Flash Internal Busy (Programming) Time Number of Flash Erase/Write Cycles Flash Retention Time
50 50 10 100 000 10
ns ns ms cycles years
Figure 76. Flash Memory - ISP Waveforms
RST TSVRL PSEN#1 TRLSX
Figure 77. Flash Memory - Internal Busy Waveforms
FBUSY bit TBHBL
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Ordering Information
Table 130. Possible Order Entries
Part Number Supply Voltage Temperature Range Package
AT89C51RE2-SLSUM 2.7V-5.5V AT89C51RE2-RLTUM AT89C51RE2-SLSEM 2.7V-5.5V AT89C51RE2-RLTEM Engineering Samples Industrial & Green
PLCC44 VQFP44 PLCC44 VQFP44
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Packaging Information
PLCC44
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STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE.
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VQFP44
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STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH). THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm.
4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.
5/ DATUM "A" AND "D" TO BE DETERMINED AT DATUM PLANE H. 6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE " f " DIMENSION AT MAXIMUM MATERIAL CONDITION . DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
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Document Revision History
Changes from 7663B to 7663C
1. Modified ordering information. 2. Various grammatical corections throughout document.
Changes from 7663C to 7663D Changes from 7663D to 7663E
1. TWI interface added.
1. Removed 64 and 68 pins package product version. 2. Minor correction on Table 69 on page 102.
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Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ...................................................................................... 3 Pin Configurations ............................................................................... 4 SFR Mapping ......................................................................................... 7 Enhanced Features ............................................................................ 13
X2 Feature .......................................................................................................... 13
Dual Data Pointer Register DPTR ..................................................... 18
Memory Architecture ........................................................................................... 21
Expanded RAM (XRAM) ..................................................................... 22
Registers............................................................................................................. 24 Extended Stack................................................................................................... 25
Flash Memory ..................................................................................... 27
General Description ............................................................................................ Features.............................................................................................................. Flash memory organization ................................................................................ On-Chip Flash memory....................................................................................... On-Chip ROM bootloader ................................................................................... Boot process....................................................................................................... Access and Operations Descriptions.................................................................. 27 27 27 28 31 32 36
Operation Cross Memory Access ..................................................... 50 Sharing Instructions ........................................................................... 50 Flash Protection from Parallel Programming .................................. 52 Bootloader Architecture .................................................................... 53
Introduction ......................................................................................................... Bootloader Description ....................................................................................... ISP Protocol Description..................................................................................... Protocol............................................................................................................... ISP Commands description ................................................................................ 53 54 56 57 61
Timers/Counters ................................................................................. 68
Timer/Counter Operations .................................................................................. 68 Timer 0................................................................................................................ 68 Timer 1................................................................................................................ 71
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Interrupt .............................................................................................................. 71 Registers............................................................................................................. 73
Timer 2 ................................................................................................. 77
Auto-Reload Mode.............................................................................................. 77 Programmable Clock-Output .............................................................................. 78 Registers............................................................................................................. 80
Programmable Counter Array PCA ................................................... 82
PCA Capture Mode............................................................................................. 16-bit Software Timer/ Compare Mode............................................................... High Speed Output Mode ................................................................................... Pulse Width Modulator Mode.............................................................................. PCA Watchdog Timer ......................................................................................... 90 90 91 92 93
Serial I/O Port ...................................................................................... 94
Framing Error Detection ..................................................................................... 94 Automatic Address Recognition.......................................................................... 95 Registers............................................................................................................. 97 Baud Rate Selection for UART 0 for Mode 1 and 3............................................ 98 Baud Rate Selection for UART 1 for Mode 1 and 3............................................ 99 UART Registers................................................................................................ 103
Interrupt System ............................................................................... 109
Registers........................................................................................................... 110 Interrupt Sources and Vector Addresses.......................................................... 117
Power Management .......................................................................... 118
Introduction ....................................................................................................... Idle Mode .......................................................................................................... Power-Down Mode ........................................................................................... Registers........................................................................................................... 118 118 118 121
Oscillator ........................................................................................... 122
Registers........................................................................................................... 122 Functional Block Diagram .................................................................................123
Hardware Watchdog Timer .............................................................. 124
Using the WDT ................................................................................................. 124 WDT During Power Down and Idle................................................................... 125
Reduced EMI Mode ........................................................................... 126 Keyboard Interface ........................................................................... 127
Registers........................................................................................................... 128
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2-wire Interface (TWI) ....................................................................... 131
Description........................................................................................................ 133 Notes ................................................................................................................ 136 Registers........................................................................................................... 146
Serial Port Interface (SPI) ................................................................ 149
Features............................................................................................................ 149 Signal Description............................................................................................. 149 Functional Description ...................................................................................... 151
Power Monitor ................................................................................... 161
Description........................................................................................................ 161
Power-off Flag ................................................................................... 163 Reset .................................................................................................. 164
Introduction ....................................................................................................... 164 Reset Input ....................................................................................................... 164 Reset Output .....................................................................................................165
Electrical Characteristics ................................................................. 166
Absolute Maximum Ratings ..............................................................................166 DC Parameters .................................................................................................166 AC Parameters ................................................................................................. 168
Ordering Information ........................................................................ 178 Packaging Information ..................................................................... 179
PLCC44 ............................................................................................................ 179 VQFP44 ............................................................................................................ 181
Document Revision History ............................................................. 183
Changes from 7663B to 7663C ........................................................................ 183 Changes from 7663C to 7663D ........................................................................ 183 Changes from 7663D to 7663E ........................................................................ 183
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
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